mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 14:40:41 +00:00
1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
112 lines
2.6 KiB
C
112 lines
2.6 KiB
C
/*
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* Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
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* Jun-jie Zhang <b18070@freescale.com>
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fsl_mdio.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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int dev_addr, int regnum, int value)
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{
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int timeout = 1000000;
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out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
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out_be32(&phyregs->miimcon, value);
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/* Memory barrier */
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mb();
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while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
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;
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}
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int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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int dev_addr, int regnum)
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{
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int value;
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int timeout = 1000000;
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/* Put the address of the phy, and the register number into MIIMADD */
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out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
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/* Clear the command register, and wait */
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out_be32(&phyregs->miimcom, 0);
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/* Memory barrier */
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mb();
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/* Initiate a read command, and wait */
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out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
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/* Memory barrier */
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mb();
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/* Wait for the the indication that the read is done */
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while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
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&& timeout--)
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;
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/* Grab the value read from the PHY */
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value = in_be32(&phyregs->miimstat);
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return value;
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}
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static int fsl_pq_mdio_reset(struct mii_dev *bus)
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{
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struct tsec_mii_mng __iomem *regs =
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(struct tsec_mii_mng __iomem *)bus->priv;
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/* Reset MII (due to new addresses) */
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out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT);
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out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
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while (in_be32(®s->miimind) & MIIMIND_BUSY)
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;
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return 0;
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}
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int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
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{
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struct tsec_mii_mng __iomem *phyregs =
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(struct tsec_mii_mng __iomem *)bus->priv;
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return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
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}
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int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
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u16 value)
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{
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struct tsec_mii_mng __iomem *phyregs =
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(struct tsec_mii_mng __iomem *)bus->priv;
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tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
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return 0;
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}
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int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FSL MDIO bus\n");
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return -1;
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}
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bus->read = tsec_phy_read;
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bus->write = tsec_phy_write;
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bus->reset = fsl_pq_mdio_reset;
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strcpy(bus->name, info->name);
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bus->priv = (void *)info->regs;
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return mdio_register(bus);
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}
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