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https://github.com/AsahiLinux/u-boot
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c00f69dbcd
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini <trini@ti.com>
87 lines
2.2 KiB
C
87 lines
2.2 KiB
C
/*
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* emif4.c
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*
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* AM33XX emif4 configuration file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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#ifdef CONFIG_SPL_BUILD
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static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
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static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
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static void config_vtp(void)
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{
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
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&vtpreg->vtp0ctrlreg);
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writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
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&vtpreg->vtp0ctrlreg);
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
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&vtpreg->vtp0ctrlreg);
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/* Poll for READY */
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while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
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VTP_CTRL_READY)
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;
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}
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void config_ddr(unsigned int pll, unsigned int ioctrl,
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const struct ddr_data *data, const struct cmd_control *ctrl,
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const struct emif_regs *regs)
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{
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enable_emif_clocks();
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ddr_pll_config(pll);
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config_vtp();
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config_cmd_ctrl(ctrl);
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config_ddr_data(0, data);
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config_ddr_data(1, data);
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config_io_ctrl(ioctrl);
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/* Set CKE to be controlled by EMIF/DDR PHY */
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writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
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/* Program EMIF instance */
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config_ddr_phy(regs);
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set_sdram_timings(regs);
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config_sdram(regs);
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}
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#endif
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