mirror of
https://github.com/AsahiLinux/u-boot
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304 lines
8.3 KiB
C
304 lines
8.3 KiB
C
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#include <asm/processor.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_NET)
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#include <config.h>
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#include <net.h>
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#include <asm/fec.h>
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#endif
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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out_be32(&scm1->mpr, 0x77777777);
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out_be32(&scm1->pacra, 0);
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out_be32(&scm1->pacrb, 0);
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out_be32(&scm1->pacrc, 0);
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out_be32(&scm1->pacrd, 0);
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out_be32(&scm1->pacre, 0);
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out_be32(&scm1->pacrf, 0);
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out_be32(&scm1->pacrg, 0);
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/* FlexBus */
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out_8(&gpio->par_be,
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GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
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GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
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out_8(&gpio->par_fbctl,
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GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
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GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
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#if !defined(CONFIG_CF_SBF)
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
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out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
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out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
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out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
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#endif
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
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/* Latch chipselect */
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out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
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out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
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out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
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out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
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out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
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out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
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out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
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out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
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out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
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out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
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out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
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out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
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out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
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out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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/*
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* now the flash base address is no longer at 0 (Newer ColdFire family
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* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
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* also move to the new location.
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*/
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if (CONFIG_SYS_CS0_BASE != 0)
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setvbr(CONFIG_SYS_CS0_BASE);
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#ifdef CONFIG_FSL_I2C
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out_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
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#endif
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFRTC
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rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
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rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
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out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
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out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
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#endif
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return (0);
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}
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void uart_port_conf(int port)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (port) {
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case 0:
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clrbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
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setbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
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break;
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case 1:
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#ifdef CONFIG_SYS_UART1_PRI_GPIO
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clrbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
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setbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
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#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
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clrbits_be16(&gpio->par_ssi,
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~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
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setbits_be16(&gpio->par_ssi,
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GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
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#endif
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break;
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case 2:
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#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
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clrbits_8(&gpio->par_timer,
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~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
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setbits_8(&gpio->par_timer,
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GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
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#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
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clrbits_8(&gpio->par_timer,
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~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
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setbits_8(&gpio->par_timer,
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GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
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#endif
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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struct fec_info_s *info = (struct fec_info_s *)dev->priv;
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if (setclear) {
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#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
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setbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC0_MDC0 |
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GPIO_PAR_FECI2C_MDIO0_MDIO0);
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else
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setbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC1_MDC1 |
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GPIO_PAR_FECI2C_MDIO1_MDIO1);
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#else
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setbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
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#endif
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
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else
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
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} else {
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clrbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
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#ifdef CONFIG_SYS_FEC_FULL_MII
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
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#else
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clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
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#endif
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} else {
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#ifdef CONFIG_SYS_FEC_FULL_MII
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
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#else
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clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
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#endif
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}
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_CF_DSPI
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void cfspi_port_conf(void)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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out_8(&gpio->par_dspi,
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GPIO_PAR_DSPI_SIN_SIN |
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GPIO_PAR_DSPI_SOUT_SOUT |
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GPIO_PAR_DSPI_SCK_SCK);
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}
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int cfspi_claim_bus(uint bus, uint cs)
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{
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dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
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return -1;
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/* Clear FIFO and resume transfer */
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clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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switch (cs) {
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case 0:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
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setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
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break;
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case 1:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
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setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
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break;
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case 2:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
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setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
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break;
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case 3:
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clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
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setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
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break;
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case 5:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
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setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
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break;
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}
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return 0;
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}
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void cfspi_release_bus(uint bus, uint cs)
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{
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dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Clear FIFO */
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clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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switch (cs) {
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case 0:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
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break;
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case 1:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
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break;
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case 2:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
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break;
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case 3:
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clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
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break;
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case 5:
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clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
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break;
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}
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}
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#endif
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