mirror of
https://github.com/AsahiLinux/u-boot
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903 lines
21 KiB
C
903 lines
21 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <div64.h>
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#include <asm/arch/sys_proto.h>
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enum pll_clocks {
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PLL1_CLOCK = 0,
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PLL2_CLOCK,
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PLL3_CLOCK,
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PLL4_CLOCK,
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PLL_CLOCKS,
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};
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struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
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[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
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[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
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[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
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#ifdef CONFIG_MX53
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[PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
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#endif
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};
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#define AHB_CLK_ROOT 133333333
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#define SZ_DEC_1M 1000000
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#define PLL_PD_MAX 16 /* Actual pd+1 */
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#define PLL_MFI_MAX 15
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#define PLL_MFI_MIN 5
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#define ARM_DIV_MAX 8
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#define IPG_DIV_MAX 4
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#define AHB_DIV_MAX 8
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#define EMI_DIV_MAX 8
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#define NFC_DIV_MAX 8
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#define MX5_CBCMR 0x00015154
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#define MX5_CBCDR 0x02888945
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struct fixed_pll_mfd {
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u32 ref_clk_hz;
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u32 mfd;
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};
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const struct fixed_pll_mfd fixed_mfd[] = {
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{CONFIG_SYS_MX5_HCLK, 24 * 16},
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};
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struct pll_param {
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u32 pd;
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u32 mfi;
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u32 mfn;
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u32 mfd;
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};
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#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
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#define PLL_FREQ_MIN(ref_clk) \
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((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
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#define MAX_DDR_CLK 420000000
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#define NFC_CLK_MAX 34000000
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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void set_usboh3_clk(void)
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{
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unsigned int reg;
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reg = readl(&mxc_ccm->cscmr1) &
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~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
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reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
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writel(reg, &mxc_ccm->cscmr1);
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reg = readl(&mxc_ccm->cscdr1);
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reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
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reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
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reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
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reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
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writel(reg, &mxc_ccm->cscdr1);
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}
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void enable_usboh3_clk(unsigned char enable)
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{
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unsigned int reg;
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reg = readl(&mxc_ccm->CCGR2);
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if (enable)
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reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
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else
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reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
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writel(reg, &mxc_ccm->CCGR2);
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}
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#ifdef CONFIG_I2C_MXC
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/* i2c_num can be from 0 - 2 */
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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u32 reg;
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u32 mask;
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if (i2c_num > 2)
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return -EINVAL;
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mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
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reg = __raw_readl(&mxc_ccm->CCGR1);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, &mxc_ccm->CCGR1);
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return 0;
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}
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#endif
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void set_usb_phy1_clk(void)
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{
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unsigned int reg;
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reg = readl(&mxc_ccm->cscmr1);
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reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
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writel(reg, &mxc_ccm->cscmr1);
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}
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void enable_usb_phy1_clk(unsigned char enable)
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{
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unsigned int reg;
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reg = readl(&mxc_ccm->CCGR4);
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if (enable)
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reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
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else
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reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
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writel(reg, &mxc_ccm->CCGR4);
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}
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void set_usb_phy2_clk(void)
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{
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unsigned int reg;
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reg = readl(&mxc_ccm->cscmr1);
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reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
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writel(reg, &mxc_ccm->cscmr1);
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}
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void enable_usb_phy2_clk(unsigned char enable)
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{
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unsigned int reg;
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reg = readl(&mxc_ccm->CCGR4);
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if (enable)
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reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
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else
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reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
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writel(reg, &mxc_ccm->CCGR4);
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}
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/*
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* Calculate the frequency of PLLn.
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*/
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static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
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{
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uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
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uint64_t refclk, temp;
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int32_t mfn_abs;
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ctrl = readl(&pll->ctrl);
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if (ctrl & MXC_DPLLC_CTL_HFSM) {
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mfn = __raw_readl(&pll->hfs_mfn);
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mfd = __raw_readl(&pll->hfs_mfd);
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op = __raw_readl(&pll->hfs_op);
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} else {
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mfn = __raw_readl(&pll->mfn);
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mfd = __raw_readl(&pll->mfd);
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op = __raw_readl(&pll->op);
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}
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mfd &= MXC_DPLLC_MFD_MFD_MASK;
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mfn &= MXC_DPLLC_MFN_MFN_MASK;
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pdf = op & MXC_DPLLC_OP_PDF_MASK;
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mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
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/* 21.2.3 */
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if (mfi < 5)
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mfi = 5;
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/* Sign extend */
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if (mfn >= 0x04000000) {
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mfn |= 0xfc000000;
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mfn_abs = -mfn;
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} else
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mfn_abs = mfn;
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refclk = infreq * 2;
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if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
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refclk *= 2;
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do_div(refclk, pdf + 1);
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temp = refclk * mfn_abs;
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do_div(temp, mfd + 1);
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ret = refclk * mfi;
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if ((int)mfn < 0)
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ret -= temp;
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else
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ret += temp;
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return ret;
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}
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/*
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* Get mcu main rate
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*/
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u32 get_mcu_main_clk(void)
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{
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u32 reg, freq;
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reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
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MXC_CCM_CACRR_ARM_PODF_OFFSET;
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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return freq / (reg + 1);
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}
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/*
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* Get the rate of peripheral's root clock.
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*/
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u32 get_periph_clk(void)
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{
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u32 reg;
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reg = __raw_readl(&mxc_ccm->cbcdr);
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if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
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return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
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reg = __raw_readl(&mxc_ccm->cbcmr);
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switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
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MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
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case 0:
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return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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case 1:
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return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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default:
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return 0;
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}
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/* NOTREACHED */
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}
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/*
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* Get the rate of ipg clock.
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*/
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static u32 get_ipg_clk(void)
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{
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uint32_t freq, reg, div;
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freq = get_ahb_clk();
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reg = __raw_readl(&mxc_ccm->cbcdr);
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div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
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MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
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return freq / div;
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}
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/*
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* Get the rate of ipg_per clock.
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*/
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static u32 get_ipg_per_clk(void)
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{
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u32 pred1, pred2, podf;
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if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
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return get_ipg_clk();
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/* Fixme: not handle what about lpm*/
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podf = __raw_readl(&mxc_ccm->cbcdr);
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pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
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MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
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pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
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MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
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podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
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MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
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return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
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}
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/*
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* Get the rate of uart clk.
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*/
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static u32 get_uart_clk(void)
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{
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unsigned int freq, reg, pred, podf;
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reg = __raw_readl(&mxc_ccm->cscmr1);
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switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
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MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
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case 0x0:
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freq = decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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break;
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case 0x1:
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freq = decode_pll(mxc_plls[PLL2_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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break;
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case 0x2:
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freq = decode_pll(mxc_plls[PLL3_CLOCK],
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CONFIG_SYS_MX5_HCLK);
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break;
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default:
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return 66500000;
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}
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reg = __raw_readl(&mxc_ccm->cscdr1);
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pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
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MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
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podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
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MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
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freq /= (pred + 1) * (podf + 1);
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return freq;
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}
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/*
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* This function returns the low power audio clock.
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*/
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static u32 get_lp_apm(void)
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{
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u32 ret_val = 0;
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u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
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if (((ccsr >> 9) & 1) == 0)
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ret_val = CONFIG_SYS_MX5_HCLK;
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else
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ret_val = ((32768 * 1024));
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return ret_val;
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}
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/*
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* get cspi clock rate.
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*/
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static u32 imx_get_cspiclk(void)
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{
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u32 ret_val = 0, pdf, pre_pdf, clk_sel;
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u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
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u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
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pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
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>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
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pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
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>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
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clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
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>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
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switch (clk_sel) {
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case 0:
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ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case 1:
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ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case 2:
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ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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default:
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ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
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break;
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}
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return ret_val;
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}
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static u32 get_axi_a_clk(void)
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{
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u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
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u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
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>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
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return get_periph_clk() / (pdf + 1);
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}
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static u32 get_axi_b_clk(void)
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{
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u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
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u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
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>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
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return get_periph_clk() / (pdf + 1);
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}
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static u32 get_emi_slow_clk(void)
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{
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u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
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u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
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u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
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>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
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if (emi_clk_sel)
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return get_ahb_clk() / (pdf + 1);
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return get_periph_clk() / (pdf + 1);
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}
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static u32 get_ddr_clk(void)
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{
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u32 ret_val = 0;
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u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
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u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
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>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
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#ifdef CONFIG_MX51
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u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
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if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
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u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
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MXC_CCM_CBCDR_DDR_PODF_OFFSET;
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ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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ret_val /= ddr_clk_podf + 1;
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return ret_val;
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}
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#endif
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switch (ddr_clk_sel) {
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case 0:
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ret_val = get_axi_a_clk();
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break;
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case 1:
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ret_val = get_axi_b_clk();
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break;
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case 2:
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ret_val = get_emi_slow_clk();
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break;
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case 3:
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ret_val = get_ahb_clk();
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break;
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default:
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break;
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}
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return ret_val;
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}
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/*
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* The API of get mxc clocks.
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*/
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_AHB_CLK:
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|
return get_ahb_clk();
|
|
case MXC_IPG_CLK:
|
|
return get_ipg_clk();
|
|
case MXC_IPG_PERCLK:
|
|
return get_ipg_per_clk();
|
|
case MXC_UART_CLK:
|
|
return get_uart_clk();
|
|
case MXC_CSPI_CLK:
|
|
return imx_get_cspiclk();
|
|
case MXC_FEC_CLK:
|
|
return decode_pll(mxc_plls[PLL1_CLOCK],
|
|
CONFIG_SYS_MX5_HCLK);
|
|
case MXC_SATA_CLK:
|
|
return get_ahb_clk();
|
|
case MXC_DDR_CLK:
|
|
return get_ddr_clk();
|
|
default:
|
|
break;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
u32 imx_get_uartclk(void)
|
|
{
|
|
return get_uart_clk();
|
|
}
|
|
|
|
|
|
u32 imx_get_fecclk(void)
|
|
{
|
|
return mxc_get_clock(MXC_IPG_CLK);
|
|
}
|
|
|
|
static int gcd(int m, int n)
|
|
{
|
|
int t;
|
|
while (m > 0) {
|
|
if (n > m) {
|
|
t = m;
|
|
m = n;
|
|
n = t;
|
|
} /* swap */
|
|
m -= n;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
/*
|
|
* This is to calculate various parameters based on reference clock and
|
|
* targeted clock based on the equation:
|
|
* t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
|
|
* This calculation is based on a fixed MFD value for simplicity.
|
|
*/
|
|
static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
|
|
{
|
|
u64 pd, mfi = 1, mfn, mfd, t1;
|
|
u32 n_target = target;
|
|
u32 n_ref = ref, i;
|
|
|
|
/*
|
|
* Make sure targeted freq is in the valid range.
|
|
* Otherwise the following calculation might be wrong!!!
|
|
*/
|
|
if (n_target < PLL_FREQ_MIN(ref) ||
|
|
n_target > PLL_FREQ_MAX(ref)) {
|
|
printf("Targeted peripheral clock should be"
|
|
"within [%d - %d]\n",
|
|
PLL_FREQ_MIN(ref) / SZ_DEC_1M,
|
|
PLL_FREQ_MAX(ref) / SZ_DEC_1M);
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
|
|
if (fixed_mfd[i].ref_clk_hz == ref) {
|
|
mfd = fixed_mfd[i].mfd;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(fixed_mfd))
|
|
return -EINVAL;
|
|
|
|
/* Use n_target and n_ref to avoid overflow */
|
|
for (pd = 1; pd <= PLL_PD_MAX; pd++) {
|
|
t1 = n_target * pd;
|
|
do_div(t1, (4 * n_ref));
|
|
mfi = t1;
|
|
if (mfi > PLL_MFI_MAX)
|
|
return -EINVAL;
|
|
else if (mfi < 5)
|
|
continue;
|
|
break;
|
|
}
|
|
/*
|
|
* Now got pd and mfi already
|
|
*
|
|
* mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
|
|
*/
|
|
t1 = n_target * pd;
|
|
do_div(t1, 4);
|
|
t1 -= n_ref * mfi;
|
|
t1 *= mfd;
|
|
do_div(t1, n_ref);
|
|
mfn = t1;
|
|
debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
|
|
ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
|
|
i = 1;
|
|
if (mfn != 0)
|
|
i = gcd(mfd, mfn);
|
|
pll->pd = (u32)pd;
|
|
pll->mfi = (u32)mfi;
|
|
do_div(mfn, i);
|
|
pll->mfn = (u32)mfn;
|
|
do_div(mfd, i);
|
|
pll->mfd = (u32)mfd;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define calc_div(tgt_clk, src_clk, limit) ({ \
|
|
u32 v = 0; \
|
|
if (((src_clk) % (tgt_clk)) <= 100) \
|
|
v = (src_clk) / (tgt_clk); \
|
|
else \
|
|
v = ((src_clk) / (tgt_clk)) + 1;\
|
|
if (v > limit) \
|
|
v = limit; \
|
|
(v - 1); \
|
|
})
|
|
|
|
#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
|
|
{ \
|
|
__raw_writel(0x1232, &pll->ctrl); \
|
|
__raw_writel(0x2, &pll->config); \
|
|
__raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
|
|
&pll->op); \
|
|
__raw_writel(fn, &(pll->mfn)); \
|
|
__raw_writel((fd) - 1, &pll->mfd); \
|
|
__raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
|
|
&pll->hfs_op); \
|
|
__raw_writel(fn, &pll->hfs_mfn); \
|
|
__raw_writel((fd) - 1, &pll->hfs_mfd); \
|
|
__raw_writel(0x1232, &pll->ctrl); \
|
|
while (!__raw_readl(&pll->ctrl) & 0x1) \
|
|
;\
|
|
}
|
|
|
|
static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
|
|
{
|
|
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
|
|
struct mxc_pll_reg *pll = mxc_plls[index];
|
|
|
|
switch (index) {
|
|
case PLL1_CLOCK:
|
|
/* Switch ARM to PLL2 clock */
|
|
__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
|
|
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
|
|
pll_param->mfi, pll_param->mfn,
|
|
pll_param->mfd);
|
|
/* Switch back */
|
|
__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
|
|
break;
|
|
case PLL2_CLOCK:
|
|
/* Switch to pll2 bypass clock */
|
|
__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
|
|
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
|
|
pll_param->mfi, pll_param->mfn,
|
|
pll_param->mfd);
|
|
/* Switch back */
|
|
__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
|
|
break;
|
|
case PLL3_CLOCK:
|
|
/* Switch to pll3 bypass clock */
|
|
__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
|
|
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
|
|
pll_param->mfi, pll_param->mfn,
|
|
pll_param->mfd);
|
|
/* Switch back */
|
|
__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
|
|
break;
|
|
case PLL4_CLOCK:
|
|
/* Switch to pll4 bypass clock */
|
|
__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
|
|
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
|
|
pll_param->mfi, pll_param->mfn,
|
|
pll_param->mfd);
|
|
/* Switch back */
|
|
__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Config CPU clock */
|
|
static int config_core_clk(u32 ref, u32 freq)
|
|
{
|
|
int ret = 0;
|
|
struct pll_param pll_param;
|
|
|
|
memset(&pll_param, 0, sizeof(struct pll_param));
|
|
|
|
/* The case that periph uses PLL1 is not considered here */
|
|
ret = calc_pll_params(ref, freq, &pll_param);
|
|
if (ret != 0) {
|
|
printf("Error:Can't find pll parameters: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return config_pll_clk(PLL1_CLOCK, &pll_param);
|
|
}
|
|
|
|
static int config_nfc_clk(u32 nfc_clk)
|
|
{
|
|
u32 reg;
|
|
u32 parent_rate = get_emi_slow_clk();
|
|
u32 div = parent_rate / nfc_clk;
|
|
|
|
if (nfc_clk <= 0)
|
|
return -EINVAL;
|
|
if (div == 0)
|
|
div++;
|
|
if (parent_rate / div > NFC_CLK_MAX)
|
|
div++;
|
|
reg = __raw_readl(&mxc_ccm->cbcdr);
|
|
reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
|
|
reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
|
|
__raw_writel(reg, &mxc_ccm->cbcdr);
|
|
while (__raw_readl(&mxc_ccm->cdhipr) != 0)
|
|
;
|
|
return 0;
|
|
}
|
|
|
|
/* Config main_bus_clock for periphs */
|
|
static int config_periph_clk(u32 ref, u32 freq)
|
|
{
|
|
int ret = 0;
|
|
struct pll_param pll_param;
|
|
|
|
memset(&pll_param, 0, sizeof(struct pll_param));
|
|
|
|
if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
|
|
ret = calc_pll_params(ref, freq, &pll_param);
|
|
if (ret != 0) {
|
|
printf("Error:Can't find pll parameters: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
switch ((__raw_readl(&mxc_ccm->cbcmr) & \
|
|
MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
|
|
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
|
|
case 0:
|
|
return config_pll_clk(PLL1_CLOCK, &pll_param);
|
|
break;
|
|
case 1:
|
|
return config_pll_clk(PLL3_CLOCK, &pll_param);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int config_ddr_clk(u32 emi_clk)
|
|
{
|
|
u32 clk_src;
|
|
s32 shift = 0, clk_sel, div = 1;
|
|
u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
|
|
u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
|
|
|
|
if (emi_clk > MAX_DDR_CLK) {
|
|
printf("Warning:DDR clock should not exceed %d MHz\n",
|
|
MAX_DDR_CLK / SZ_DEC_1M);
|
|
emi_clk = MAX_DDR_CLK;
|
|
}
|
|
|
|
clk_src = get_periph_clk();
|
|
/* Find DDR clock input */
|
|
clk_sel = (cbcmr >> 10) & 0x3;
|
|
switch (clk_sel) {
|
|
case 0:
|
|
shift = 16;
|
|
break;
|
|
case 1:
|
|
shift = 19;
|
|
break;
|
|
case 2:
|
|
shift = 22;
|
|
break;
|
|
case 3:
|
|
shift = 10;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((clk_src % emi_clk) < 10000000)
|
|
div = clk_src / emi_clk;
|
|
else
|
|
div = (clk_src / emi_clk) + 1;
|
|
if (div > 8)
|
|
div = 8;
|
|
|
|
cbcdr = cbcdr & ~(0x7 << shift);
|
|
cbcdr |= ((div - 1) << shift);
|
|
__raw_writel(cbcdr, &mxc_ccm->cbcdr);
|
|
while (__raw_readl(&mxc_ccm->cdhipr) != 0)
|
|
;
|
|
__raw_writel(0x0, &mxc_ccm->ccdr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This function assumes the expected core clock has to be changed by
|
|
* modifying the PLL. This is NOT true always but for most of the times,
|
|
* it is. So it assumes the PLL output freq is the same as the expected
|
|
* core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
|
|
* In the latter case, it will try to increase the presc value until
|
|
* (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
|
|
* calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
|
|
* on the targeted PLL and reference input clock to the PLL. Lastly,
|
|
* it sets the register based on these values along with the dividers.
|
|
* Note 1) There is no value checking for the passed-in divider values
|
|
* so the caller has to make sure those values are sensible.
|
|
* 2) Also adjust the NFC divider such that the NFC clock doesn't
|
|
* exceed NFC_CLK_MAX.
|
|
* 3) IPU HSP clock is independent of AHB clock. Even it can go up to
|
|
* 177MHz for higher voltage, this function fixes the max to 133MHz.
|
|
* 4) This function should not have allowed diag_printf() calls since
|
|
* the serial driver has been stoped. But leave then here to allow
|
|
* easy debugging by NOT calling the cyg_hal_plf_serial_stop().
|
|
*/
|
|
int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
|
|
{
|
|
freq *= SZ_DEC_1M;
|
|
|
|
switch (clk) {
|
|
case MXC_ARM_CLK:
|
|
if (config_core_clk(ref, freq))
|
|
return -EINVAL;
|
|
break;
|
|
case MXC_PERIPH_CLK:
|
|
if (config_periph_clk(ref, freq))
|
|
return -EINVAL;
|
|
break;
|
|
case MXC_DDR_CLK:
|
|
if (config_ddr_clk(freq))
|
|
return -EINVAL;
|
|
break;
|
|
case MXC_NFC_CLK:
|
|
if (config_nfc_clk(freq))
|
|
return -EINVAL;
|
|
break;
|
|
default:
|
|
printf("Warning:Unsupported or invalid clock type\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MX53
|
|
/*
|
|
* The clock for the external interface can be set to use internal clock
|
|
* if fuse bank 4, row 3, bit 2 is set.
|
|
* This is an undocumented feature and it was confirmed by Freescale's support:
|
|
* Fuses (but not pins) may be used to configure SATA clocks.
|
|
* Particularly the i.MX53 Fuse_Map contains the next information
|
|
* about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
|
|
* '00' - 100MHz (External)
|
|
* '01' - 50MHz (External)
|
|
* '10' - 120MHz, internal (USB PHY)
|
|
* '11' - Reserved
|
|
*/
|
|
void mxc_set_sata_internal_clock(void)
|
|
{
|
|
u32 *tmp_base =
|
|
(u32 *)(IIM_BASE_ADDR + 0x180c);
|
|
|
|
set_usb_phy1_clk();
|
|
|
|
writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Dump some core clockes.
|
|
*/
|
|
int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
u32 freq;
|
|
|
|
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
|
|
printf("PLL1 %8d MHz\n", freq / 1000000);
|
|
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
|
|
printf("PLL2 %8d MHz\n", freq / 1000000);
|
|
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
|
|
printf("PLL3 %8d MHz\n", freq / 1000000);
|
|
#ifdef CONFIG_MX53
|
|
freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
|
|
printf("PLL4 %8d MHz\n", freq / 1000000);
|
|
#endif
|
|
|
|
printf("\n");
|
|
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
|
|
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
|
|
printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
|
|
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/***************************************************/
|
|
|
|
U_BOOT_CMD(
|
|
clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
|
|
"display clocks",
|
|
""
|
|
);
|