u-boot/include/micrel.h
Philippe Schenker f72e48ba4d board: apalis_imx6: Add KSZ9131 phy skew settings
This patch adds skew register settings for KSZ9131. It checks first
which phy is on the board and then applies the correct skew settings.

Skew settings calculation for the KSZ9131:
The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All
PCB traces where routed exactly the same length so we can calculate
the skew settings without taking the length into consideration. The
traces are all length matched.

RXC skew (PHY to MAC):
- We use the 2ns DLL controlled delay on the PHY
- We do not use the skew registers

This results in the following values:

		RXC
PHY fixed Delay	2000ps
PHY Added Delay	0ps
T_setup_R min	2.00ns
T_setup_R typ	2.00ns
T_setup_R max	2.00ns
T_hold_R min	1.60ns
T_hold_R typ	2.00ns
T_hold_R max	2.40ns

That means we are well within RGMII specs.

TXC skew (MAC to PHY):
- We use the 2ns DLL controlled delay on the PHY
- We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew
  register in a resulting ~1.4ns delay.

This results in the following values under consideration of the
tolerances:

		TXC min	TXC typ	TXC max
MAC min		-100ps	-100ps	-100ps
MAC max		900ps	900ps	900ps
PHY fixed Delay	2000ps	2000ps	2000ps
PHY added Delay	-340ps	-600ps	-859ps
T_setup_T min	1.56ns	1.30ns	1.04ns
T_setup_T typ	2.06ns	1.80ns	1.54ns
T_setup_T max	2.56ns	2.30ns	2.04ns
T_hold_T min	1.04ns	1.30ns	1.56ns
T_hold_T typ	1.94ns	2.20ns	2.46ns
T_hold_T max	2.84ns	3.10ns	3.36ns

This shows that T_hold_T min and T_setup_T min times are out of spec
for RGMII timing. However the KSZ9131 has a minimal value for this time
of 0.8ns which is met under all circumstances.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01 13:46:22 +02:00

50 lines
1.6 KiB
C

#ifndef _MICREL_H
#define MII_KSZ9021_EXT_COMMON_CTRL 0x100
#define MII_KSZ9021_EXT_STRAP_STATUS 0x101
#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
#define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
#define MII_KSZ9021_EXT_ANALOG_TEST 0x107
/* Register operations */
#define MII_KSZ9031_MOD_REG 0x0000
/* Data operations */
#define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
#define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000
#define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000
#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4
#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
#define MII_KSZ9131_RXTXDLL_BYPASS BIT(12)
#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL 0x4c
#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL 0x4d
#define PHY_ID_KSZ9031 0x00221620
#define PHY_ID_KSZ9131 0x00221640
/* Registers */
#define MMD_ACCESS_CONTROL 0xd
#define MMD_ACCESS_REG_DATA 0xe
struct phy_device;
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
int regnum, u16 mode, u16 val);
int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
int regnum, u16 mode);
int ksz9xx1_phy_get_id(struct phy_device *phydev);
#endif