JC Kuo d491dc09e4 t210: do not enable PLLE and UPHY PLL HW PWRSEQ ... This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>		2020-04-02 14:30:01 -07:00
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clock.c	t210: do not enable PLLE and UPHY PLL HW PWRSEQ	2020-04-02 14:30:01 -07:00
funcmux.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
Kconfig	arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET	2019-07-10 22:37:23 +09:00
Makefile	ARM: tegra: switch Tegra210 to common XUSB padctl	2015-11-12 09:21:06 -07:00
pinmux.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
xusb-padctl.c	t210: do not enable PLLE and UPHY PLL HW PWRSEQ	2020-04-02 14:30:01 -07:00