mirror of
https://github.com/AsahiLinux/u-boot
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effcf067df
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
156 lines
2.8 KiB
C
156 lines
2.8 KiB
C
/*
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* From Coreboot file of the same name
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*
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* Copyright (C) 2012 Chromium OS Authors
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/* mailbox 0: header */
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__packed struct opregion_header {
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u8 signature[16];
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u32 size;
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u32 version;
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u8 sbios_version[32];
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u8 vbios_version[16];
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u8 driver_version[16];
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u32 mailboxes;
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u8 reserved[164];
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};
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#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
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#define IGD_OPREGION_VERSION 2
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#define IGD_MBOX1 (1 << 0)
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#define IGD_MBOX2 (1 << 1)
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#define IGD_MBOX3 (1 << 2)
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#define IGD_MBOX4 (1 << 3)
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#define IGD_MBOX5 (1 << 4)
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#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
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IGD_MBOX4 | IGD_MBOX5)
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#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
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#define SBIOS_VERSION_SIZE 32
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/* mailbox 1: public acpi methods */
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__packed struct opregion_mailbox1 {
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u32 drdy;
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u32 csts;
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u32 cevt;
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u8 reserved1[20];
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u32 didl[8];
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u32 cpdl[8];
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u32 cadl[8];
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u32 nadl[8];
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u32 aslp;
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u32 tidx;
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u32 chpd;
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u32 clid;
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u32 cdck;
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u32 sxsw;
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u32 evts;
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u32 cnot;
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u32 nrdy;
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u8 reserved2[60];
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};
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/* mailbox 2: software sci interface */
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__packed struct opregion_mailbox2 {
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u32 scic;
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u32 parm;
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u32 dslp;
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u8 reserved[244];
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};
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/* mailbox 3: power conservation */
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__packed struct opregion_mailbox3 {
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u32 ardy;
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u32 aslc;
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u32 tche;
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u32 alsi;
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u32 bclp;
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u32 pfit;
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u32 cblv;
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u16 bclm[20];
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u32 cpfm;
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u32 epfm;
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u8 plut[74];
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u32 pfmb;
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u32 ccdv;
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u32 pcft;
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u8 reserved[94];
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};
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#define IGD_BACKLIGHT_BRIGHTNESS 0xff
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#define IGD_INITIAL_BRIGHTNESS 0x64
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#define IGD_FIELD_VALID (1 << 31)
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#define IGD_WORD_FIELD_VALID (1 << 15)
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#define IGD_PFIT_STRETCH 6
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/* mailbox 4: vbt */
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__packed struct {
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u8 gvd1[7168];
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} opregion_vbt_t;
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/* IGD OpRegion */
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__packed struct igd_opregion {
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opregion_header_t header;
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opregion_mailbox1_t mailbox1;
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opregion_mailbox2_t mailbox2;
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opregion_mailbox3_t mailbox3;
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opregion_vbt_t vbt;
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};
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/* Intel Video BIOS (Option ROM) */
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__packed struct optionrom_header {
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u16 signature;
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u8 size;
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u8 reserved[21];
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u16 pcir_offset;
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u16 vbt_offset;
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};
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#define OPROM_SIGNATURE 0xaa55
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__packed struct optionrom_pcir {
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u32 signature;
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u16 vendor;
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u16 device;
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u16 reserved1;
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u16 length;
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u8 revision;
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u8 classcode[3];
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u16 imagelength;
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u16 coderevision;
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u8 codetype;
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u8 indicator;
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u16 reserved2;
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};
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__packed struct optionrom_vbt {
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u8 hdr_signature[20];
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u16 hdr_version;
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u16 hdr_size;
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u16 hdr_vbt_size;
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u8 hdr_vbt_checksum;
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u8 hdr_reserved;
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u32 hdr_vbt_datablock;
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u32 hdr_aim[4];
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u8 datahdr_signature[16];
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u16 datahdr_version;
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u16 datahdr_size;
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u16 datahdr_datablocksize;
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u8 coreblock_id;
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u16 coreblock_size;
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u16 coreblock_biossize;
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u8 coreblock_biostype;
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u8 coreblock_releasestatus;
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u8 coreblock_hwsupported;
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u8 coreblock_integratedhw;
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u8 coreblock_biosbuild[4];
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u8 coreblock_biossignon[155];
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};
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#define VBT_SIGNATURE 0x54425624
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