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https://github.com/AsahiLinux/u-boot
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9973e3c614
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
203 lines
6.1 KiB
C
203 lines
6.1 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include "eric.h"
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#include <asm/processor.h>
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#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */
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#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
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#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
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#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
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void sdram_init(void);
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the ERIC board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive
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| IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive
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| IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive
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| indicates NO Power or HOST RESET active
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| check GPIO7 (HOST RESET#) and GPIO8 (NO Power#)
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| for real IRQ source
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| IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
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| -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
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| PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
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| else tristate)
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| Note for ERIC board:
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| An interrupt taken for the HOST (IRQ 28) indicates that
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| the HOST wrote a "1" to one of the following locations
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| - VGA CRT_GPIO0 (if R1216 is loaded)
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| - VGA CRT_GPIO1 (if R1217 is loaded)
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+-------------------------------------------------------------------------*/
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */
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mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
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mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
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out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
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out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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char *e;
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puts ("Board: ");
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if (!s || strncmp (s, "ERIC", 9)) {
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puts ("### No HW ID - assuming ERIC");
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} else {
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for (e = s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for (; s < e; ++s) {
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putc (*s);
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}
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/*
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initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
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the necessary info for SDRAM controller configuration
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*/
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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#ifndef CONFIG_ERIC
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int i;
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unsigned char datain[128];
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int TotalSize;
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#endif
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/*
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* ToDo: Move the asm init routine sdram_init() to this C file,
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* or even better use some common ppc4xx code available
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* in cpu/ppc4xx
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*/
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sdram_init();
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#ifdef CONFIG_ERIC
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/*
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* we have no EEPROM on ERIC
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* so let init.S do the init job for SDRAM
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* and simply return 32MByte here
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*/
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return (CFG_SDRAM_SIZE * 1024 * 1024);
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#else
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/* Read Serial Presence Detect Information */
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for (i = 0; i < 128; i++)
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datain[i] = 127;
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i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128);
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printf ("\nReading DIMM...\n");
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#if 0
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for (i = 0; i < 128; i++) {
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printf ("%d=0x%x ", i, datain[i]);
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if (((i + 1) % 10) == 0)
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printf ("\n");
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}
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printf ("\n");
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#endif
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/*****************************/
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/* Retrieve interesting data */
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/*****************************/
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/* size of a SDRAM bank */
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/* Number of bytes per side / number of banks per side */
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if (datain[31] == 0x08)
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TotalSize = 32;
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else if (datain[31] == 0x10)
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TotalSize = 64;
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else {
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printf ("IIC READ ERROR!!!\n");
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TotalSize = 32;
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}
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/* single-sided DIMM or double-sided DIMM? */
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if (datain[5] != 1) {
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/* double-sided DIMM => SDRAM banks 0..3 are valid */
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printf ("double-sided DIMM\n");
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TotalSize *= 2;
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}
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/* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */
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else {
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printf ("single-sided DIMM\n");
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}
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/* return size in Mb unit => *(1024*1024) */
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return (TotalSize * 1024 * 1024);
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#endif
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: xxx MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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