mirror of
https://github.com/AsahiLinux/u-boot
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275 lines
6.5 KiB
C
275 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Armadeus Systems
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <environment.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_FEC_MXC
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#include <miiphy.h>
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#define MDIO_PAD_CTRL ( \
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PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm \
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)
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#define ENET_PAD_CTRL_PU ( \
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PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm \
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)
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#define ENET_PAD_CTRL_PD ( \
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm \
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)
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#define ENET_CLK_PAD_CTRL ( \
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PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
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)
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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/* PHY Int */
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MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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/* PHY Reset */
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MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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};
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int board_phy_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct gpio_desc rst;
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int ret;
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/* Use 50M anatop loopback REF_CLK1 for ENET1,
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* clear gpr1[13], set gpr1[17] */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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enable_enet_clk(1);
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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ret = dm_gpio_lookup_name("GPIO4_2", &rst);
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if (ret) {
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printf("Cannot get GPIO4_2\n");
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return ret;
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}
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ret = dm_gpio_request(&rst, "phy-rst");
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if (ret) {
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printf("Cannot request GPIO4_2\n");
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return ret;
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}
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dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
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dm_gpio_set_value(&rst, 0);
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udelay(1000);
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dm_gpio_set_value(&rst, 1);
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return fecmxc_initialize(bis);
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}
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#endif /* CONFIG_FEC_MXC */
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int __weak opos6ul_board_late_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned reg = readl(&psrc->sbmr2);
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/* In bootstrap don't use the env vars */
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if (((reg & 0x3000000) >> 24) == 0x1) {
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set_default_env(NULL, 0);
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env_set("preboot", "");
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}
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return opos6ul_board_late_init();
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <asm/arch/mx6-ddr.h>
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#include <linux/libfdt.h>
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#include <spl.h>
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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};
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_odt0 = 0x00000030,
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.dram_odt1 = 0x00000030,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000008,
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.dram_sdqs0 = 0x00000038,
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.dram_sdqs1 = 0x00000030,
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.dram_reset = 0x00000030,
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00070007,
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.p0_mpdgctrl0 = 0x41490145,
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.p0_mprddlctl = 0x40404546,
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.p0_mpwrdlctl = 0x4040524D,
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};
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struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs_density = 20,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refreshes commands per refresh cycle */
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1500,
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.trcmin = 5250,
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.trasmin = 3750,
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};
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void board_boot_order(u32 *spl_boot_list)
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{
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unsigned int bmode = readl(&src_base->sbmr2);
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if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
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spl_boot_list[0] = BOOT_DEVICE_UART;
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else
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spl_boot_list[0] = spl_boot_device();
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}
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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writel(0xFFFFFFFF, &ccm->CCGR7);
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}
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static void spl_dram_init(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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int reg = readl(&fuse->gp1);
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/* 512MB of RAM */
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if (reg & 0x1) {
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mem_ddr.density = 4;
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mem_ddr.rowaddr = 15;
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mem_ddr.trcd = 1375;
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mem_ddr.trcmin = 4875;
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mem_ddr.trasmin = 3500;
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}
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void spl_board_init(void)
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{
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preloader_console_init();
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}
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* setup GP timer */
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timer_init();
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/* DDR initialization */
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spl_dram_init();
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}
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#endif /* CONFIG_SPL_BUILD */
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