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The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
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.. | ||
ap.h | ||
board.h | ||
clk_rst.h | ||
clock.h | ||
funcmux.h | ||
fuse.h | ||
gp_padctrl.h | ||
gpio.h | ||
mmc.h | ||
pmc.h | ||
scu.h | ||
sys_proto.h | ||
tegra.h | ||
tegra_i2c.h | ||
tegra_mmc.h | ||
timer.h | ||
uart.h | ||
usb.h | ||
warmboot.h |