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https://github.com/AsahiLinux/u-boot
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17a42abb40
Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
222 lines
6.5 KiB
C
222 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx ZynqMP SoC Tap Delay Programming
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*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/delay.h>
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#include <mmc.h>
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#define SD_DLL_CTRL 0xFF180358
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#define SD_ITAP_DLY 0xFF180314
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#define SD_OTAP_DLY 0xFF180318
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#define SD0_DLL_RST_MASK 0x00000004
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#define SD0_DLL_RST 0x00000004
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#define SD1_DLL_RST_MASK 0x00040000
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#define SD1_DLL_RST 0x00040000
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#define SD0_ITAPCHGWIN_MASK 0x00000200
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#define SD0_ITAPCHGWIN 0x00000200
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#define SD1_ITAPCHGWIN_MASK 0x02000000
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#define SD1_ITAPCHGWIN 0x02000000
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#define SD0_ITAPDLYENA_MASK 0x00000100
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#define SD0_ITAPDLYENA 0x00000100
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#define SD1_ITAPDLYENA_MASK 0x01000000
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#define SD1_ITAPDLYENA 0x01000000
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#define SD0_ITAPDLYSEL_MASK 0x000000FF
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#define SD0_ITAPDLYSEL_HSD 0x00000015
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#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
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#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
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#define SD1_ITAPDLYSEL_MASK 0x00FF0000
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#define SD1_ITAPDLYSEL_HSD 0x00150000
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#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
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#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
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#define SD0_OTAPDLYSEL_MASK 0x0000003F
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#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
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#define SD0_OTAPDLYSEL_SD_HSD 0x00000005
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#define SD0_OTAPDLYSEL_SDR50 0x00000003
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#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
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#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
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#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
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#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
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#define SD1_OTAPDLYSEL_MASK 0x003F0000
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#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
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#define SD1_OTAPDLYSEL_SD_HSD 0x00050000
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#define SD1_OTAPDLYSEL_SDR50 0x00030000
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#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
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#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
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#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
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#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
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#define MMC_BANK2 0x2
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void zynqmp_dll_reset(u8 deviceid)
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{
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/* Issue DLL Reset */
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
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SD0_DLL_RST);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
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SD1_DLL_RST);
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mdelay(1);
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/* Release DLL Reset */
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
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}
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static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program OTAP */
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if (bank == MMC_BANK2)
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SDR104_B2);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SDR104_B0);
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} else {
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/* Program OTAP */
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if (bank == MMC_BANK2)
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SDR104_B2);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SDR104_B0);
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}
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}
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static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
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SD0_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
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SD0_ITAPDLYENA);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
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SD0_ITAPDLYSEL_HSD);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_MMC_HS)
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_MMC_HSD);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SD_HSD);
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} else {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
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SD1_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
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SD1_ITAPDLYENA);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
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SD1_ITAPDLYSEL_HSD);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_MMC_HS)
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_MMC_HSD);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SD_HSD);
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}
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}
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static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
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SD0_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
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SD0_ITAPDLYENA);
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
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SD0_ITAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
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SD0_ITAPDLYSEL_MMC_DDR50);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_MMC_DDR50);
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} else {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
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SD1_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
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SD1_ITAPDLYENA);
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
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SD1_ITAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
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SD1_ITAPDLYSEL_MMC_DDR50);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_MMC_DDR50);
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}
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}
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static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program OTAP */
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SDR50);
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} else {
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/* Program OTAP */
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SDR50);
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}
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}
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void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
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SD0_DLL_RST);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
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SD1_DLL_RST);
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switch (timing) {
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case MMC_TIMING_UHS_SDR25:
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arasan_zynqmp_tap_hs(deviceid, timing, bank);
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break;
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case MMC_TIMING_UHS_SDR50:
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arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
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break;
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case MMC_TIMING_UHS_DDR50:
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arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
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break;
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}
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
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}
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