mirror of
https://github.com/AsahiLinux/u-boot
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0adf8d3548
Intel has invented yet another binary blob which firmware is required to run. This is run after SDRAM is ready. It is linked to load at a particular address, typically 0, but is a relocatable ELF so can be moved if required. Add support for this in the build system. The file should be placed in the board directory, and called refcode.elf. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
290 lines
6.2 KiB
C
290 lines
6.2 KiB
C
/*
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* Copyright (c) 2014 The Chromium OS Authors.
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*
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* Part of this file is adapted from coreboot
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* src/arch/x86/include/arch/cpu.h and
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* src/arch/x86/lib/cpu.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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enum {
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X86_VENDOR_INVALID = 0,
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X86_VENDOR_INTEL,
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X86_VENDOR_CYRIX,
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X86_VENDOR_AMD,
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X86_VENDOR_UMC,
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X86_VENDOR_NEXGEN,
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X86_VENDOR_CENTAUR,
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X86_VENDOR_RISE,
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X86_VENDOR_TRANSMETA,
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X86_VENDOR_NSC,
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X86_VENDOR_SIS,
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X86_VENDOR_ANY = 0xfe,
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X86_VENDOR_UNKNOWN = 0xff
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};
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/* Global descriptor table (GDT) bits */
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enum {
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GDT_4KB = 1ULL << 55,
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GDT_32BIT = 1ULL << 54,
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GDT_LONG = 1ULL << 53,
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GDT_PRESENT = 1ULL << 47,
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GDT_NOTSYS = 1ULL << 44,
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GDT_CODE = 1ULL << 43,
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GDT_LIMIT_LOW_SHIFT = 0,
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GDT_LIMIT_LOW_MASK = 0xffff,
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GDT_LIMIT_HIGH_SHIFT = 48,
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GDT_LIMIT_HIGH_MASK = 0xf,
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GDT_BASE_LOW_SHIFT = 16,
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GDT_BASE_LOW_MASK = 0xffff,
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GDT_BASE_HIGH_SHIFT = 56,
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GDT_BASE_HIGH_MASK = 0xf,
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};
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/*
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* System controllers in an x86 system. We mostly need to just find these and
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* use them on PCI. At some point these might have their own uclass (e.g.
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* UCLASS_VIDEO for the GMA device).
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*/
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enum {
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X86_NONE,
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X86_SYSCON_ME, /* Intel Management Engine */
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X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
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X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
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};
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struct cpuid_result {
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uint32_t eax;
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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};
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/*
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* Generic CPUID function
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*/
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static inline struct cpuid_result cpuid(int op)
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{
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struct cpuid_result result;
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asm volatile(
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"mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%ebx, %%esi;"
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"mov %%edi, %%ebx;"
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: "=a" (result.eax),
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"=S" (result.ebx),
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"=c" (result.ecx),
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"=d" (result.edx)
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: "0" (op)
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: "edi");
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return result;
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}
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/*
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* Generic Extended CPUID function
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*/
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static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
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{
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struct cpuid_result result;
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asm volatile(
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"mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%ebx, %%esi;"
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"mov %%edi, %%ebx;"
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: "=a" (result.eax),
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"=S" (result.ebx),
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"=c" (result.ecx),
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"=d" (result.edx)
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: "0" (op), "2" (ecx)
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: "edi");
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return result;
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%edi, %%ebx;"
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: "=a" (eax)
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: "0" (op)
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: "ecx", "edx", "edi");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%ebx, %%esi;"
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"mov %%edi, %%ebx;"
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: "=a" (eax), "=S" (ebx)
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: "0" (op)
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: "ecx", "edx", "edi");
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%edi, %%ebx;"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "edx", "edi");
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%edi, %%ebx;"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "ecx", "edi");
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return edx;
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}
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(uint32_t flag)
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{
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uint32_t f1, f2;
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asm(
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"pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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static inline void mfence(void)
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{
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__asm__ __volatile__("mfence" : : : "memory");
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}
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/**
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* cpu_enable_paging_pae() - Enable PAE-paging
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*
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* @cr3: Value to set in cr3 (PDPT or PML4T)
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*/
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void cpu_enable_paging_pae(ulong cr3);
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/**
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* cpu_disable_paging_pae() - Disable paging and PAE
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*/
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void cpu_disable_paging_pae(void);
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/**
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* cpu_has_64bit() - Check if the CPU has 64-bit support
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*
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* @return 1 if this CPU supports long mode (64-bit), 0 if not
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*/
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int cpu_has_64bit(void);
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/**
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* cpu_vendor_name() - Get CPU vendor name
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*
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* @vendor: CPU vendor enumeration number
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*
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* @return: Address to hold the CPU vendor name string
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*/
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const char *cpu_vendor_name(int vendor);
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#define CPU_MAX_NAME_LEN 49
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/**
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* cpu_get_name() - Get the name of the current cpu
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*
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* @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
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* @return pointer to name, which will likely be a few bytes after the start
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* of @name
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* \0 terminator
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*/
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char *cpu_get_name(char *name);
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/**
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* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
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*
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* The kernel is uncompressed and the 64-bit entry point is expected to be
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* at @target.
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*
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* This function is used internally - see cpu_jump_to_64bit() for a more
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* useful function.
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*
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* @pgtable: Address of 24KB area containing the page table
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* @setup_base: Pointer to the setup.bin information for the kernel
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* @target: Pointer to the start of the kernel image
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*/
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void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
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/**
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* cpu_call32() - Jump to a 32-bit entry point
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*
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* @code_seg32: 32-bit code segment to use (GDT offset, e.g. 0x20)
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* @target: Pointer to the start of the 32-bit U-Boot image/entry point
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* @table: Pointer to start of info table to pass to U-Boot
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*/
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void cpu_call32(ulong code_seg32, ulong target, ulong table);
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/**
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* cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
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*
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* The kernel is uncompressed and the 64-bit entry point is expected to be
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* at @target.
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*
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* @setup_base: Pointer to the setup.bin information for the kernel
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* @target: Pointer to the start of the kernel image
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*/
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int cpu_jump_to_64bit(ulong setup_base, ulong target);
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/**
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* cpu_get_family_model() - Get the family and model for the CPU
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*
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* @return the CPU ID masked with 0x0fff0ff0
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*/
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u32 cpu_get_family_model(void);
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/**
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* cpu_get_stepping() - Get the stepping value for the CPU
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*
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* @return the CPU ID masked with 0xf
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*/
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u32 cpu_get_stepping(void);
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/**
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* cpu_run_reference_code() - Run the platform reference code
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*
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* Some platforms require a binary blob to be executed once SDRAM is
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* available. This is used to set up various platform features, such as the
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* platform controller hub (PCH). This function should be implemented by the
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* CPU-specific code.
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*
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* @return 0 on success, -ve on failure
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*/
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int cpu_run_reference_code(void);
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#endif
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