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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
174 lines
3.7 KiB
C
174 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RCar Gen3 CPG MSSR driver
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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/*
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen2, R-Car Gen3, and RZ/G1.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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/*
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* Module Stop Status Register offsets
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*/
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static const u16 mstpsr[] = {
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0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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#define MSTPSR(i) mstpsr[i]
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/*
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* System Module Stop Control Register offsets
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*/
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static const u16 smstpcr[] = {
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0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
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0x990, 0x994, 0x998, 0x99C,
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};
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#define SMSTPCR(i) smstpcr[i]
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) (smstpcr[i] - 0x20)
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/* Modem Module Stop Control Register offsets (r8a73a4) */
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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bool renesas_clk_is_mod(struct clk *clk)
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{
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return (clk->id >> 16) == CPG_MOD;
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}
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int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
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const struct mssr_mod_clk **mssr)
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{
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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for (i = 0; i < info->mod_clk_size; i++) {
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if (info->mod_clk[i].id !=
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(info->mod_clk_base + MOD_CLK_PACK(clkid)))
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continue;
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*mssr = &info->mod_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
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const struct cpg_core_clk **core)
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{
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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for (i = 0; i < info->core_clk_size; i++) {
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if (info->core_clk[i].id != clkid)
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continue;
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*core = &info->core_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
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struct clk *parent)
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{
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const struct cpg_core_clk *core;
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const struct mssr_mod_clk *mssr;
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int ret;
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if (renesas_clk_is_mod(clk)) {
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ret = renesas_clk_get_mod(clk, info, &mssr);
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if (ret)
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return ret;
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parent->id = mssr->parent;
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} else {
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ret = renesas_clk_get_core(clk, info, &core);
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if (ret)
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return ret;
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if (core->type == CLK_TYPE_IN)
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parent->id = ~0; /* Top-level clock */
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else
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parent->id = core->parent;
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}
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parent->dev = clk->dev;
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return 0;
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}
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int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
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{
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const unsigned long clkid = clk->id & 0xffff;
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const unsigned int reg = clkid / 100;
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const unsigned int bit = clkid % 100;
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const u32 bitmask = BIT(bit);
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if (!renesas_clk_is_mod(clk))
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return -EINVAL;
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debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
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clkid, reg, bit, enable ? "ON" : "OFF");
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if (enable) {
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clrbits_le32(base + SMSTPCR(reg), bitmask);
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return wait_for_bit_le32(base + MSTPSR(reg),
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bitmask, 0, 100, 0);
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} else {
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setbits_le32(base + SMSTPCR(reg), bitmask);
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return 0;
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}
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}
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int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
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{
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unsigned int i;
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/* Stop TMU0 */
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clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
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/* Stop module clock */
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for (i = 0; i < info->mstp_table_size; i++) {
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clrsetbits_le32(base + SMSTPCR(i),
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info->mstp_table[i].sdis,
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info->mstp_table[i].sen);
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clrsetbits_le32(base + RMSTPCR(i),
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info->mstp_table[i].rdis,
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info->mstp_table[i].ren);
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}
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return 0;
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}
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