Dave Gerlach d3c56e2a82 clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write ... There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca1 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>		2021-09-17 14:47:03 -04:00
..
altera	drivers: clk: Add memory clock driver for Intel N5X device	2021-08-25 12:55:13 +08:00
analogbits	clk: sifive: Sync-up WRPLL library with upstream Linux	2019-07-19 14:24:51 +08:00
aspeed	clk: Update drivers to use -EINVAL	2021-04-06 16:33:19 +12:00
at91	Merge branch '2021-02-02-drop-asm_global_data-when-unused'	2021-02-15 10:16:45 -05:00
exynos	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
imx	clk: imx8mm: Add SPI clocks	2021-07-10 16:03:01 +02:00
intel	clk: x86: Correct the driver name	2021-01-30 14:25:41 -07:00
mediatek	clk: mediatek: Add MT8183 clock driver	2021-01-18 15:14:13 -05:00
meson	clk: meson-g12a: add PCIe gates	2021-04-19 16:59:33 +02:00
microchip	clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag	2021-04-08 15:37:30 +08:00
mtmips	clk: add clock driver for MediaTek MT7620 SoC	2021-01-24 21:39:26 +01:00
mvebu	clk: armada-37xx: Set DM_FLAG_PRE_RELOC	2021-07-08 16:40:52 +02:00
owl	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
renesas	clk: renesas: Add R8A779A0 clock tables	2021-06-24 20:22:17 +02:00
rockchip	rockchip: px30: Support configure SFC	2021-08-12 09:34:11 +08:00
sifive	drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'	2021-07-06 13:47:33 +08:00
sunxi	clk: sunxi: h6: Add XHCI clocks	2021-04-16 01:12:59 +01:00
tegra	common: Drop log.h from common header	2020-05-18 21:19:18 -04:00
ti	clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write	2021-09-17 14:47:03 -04:00
uniphier	clk: uniphier: Add PCIe clock entry	2021-07-14 16:48:05 -04:00
clk-cdce9xx.c	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
clk-composite.c	clk: Return -ENOSYS when system call is not available	2021-04-06 16:33:19 +12:00
clk-divider.c	clk: export generic routines	2021-01-12 10:21:41 +05:30
clk-fixed-factor.c	clk: set flags in the ccf registration routines	2020-08-24 11:03:26 +02:00
clk-gate.c	clk: set flags in the ccf registration routines	2020-08-24 11:03:26 +02:00
clk-hsdk-cgu.c	clk: Update drivers to use -EINVAL	2021-04-06 16:33:19 +12:00
clk-mux.c	clk: ccf: replace the get_rate helper	2020-10-22 11:26:14 -04:00
clk-uclass.c	clk: Detect failure to set defaults	2021-07-15 18:42:40 -04:00
clk-xlnx-clock-wizard.c	clk: zynq: Add clock wizard driver	2021-06-23 09:48:35 +02:00
clk.c	dm: core: Access device flags through functions	2021-01-05 12:24:41 -07:00
clk_bcm6345.c	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
clk_boston.c	dm: treewide: Rename ofdata_to_platdata() to of_to_plat()	2020-12-13 16:51:09 -07:00
clk_fixed_factor.c	dm: treewide: Rename ofdata_to_platdata() to of_to_plat()	2020-12-13 16:51:09 -07:00
clk_fixed_rate.c	clk: fixed_rate: add API for directly registering fixed rate clocks	2021-06-11 16:34:52 +05:30
clk_kendryte.c	clk: k210: Move k210 clock out of its own subdirectory	2021-06-17 09:40:58 +08:00
clk_octeon.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
clk_pic32.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
clk_sandbox.c	clk: sandbox: Create a special fixed-rate driver	2021-03-26 17:03:08 +13:00
clk_sandbox_ccf.c	clk: set flags in the ccf registration routines	2020-08-24 11:03:26 +02:00
clk_sandbox_test.c	clk: sandbox: Move priv/plat data to a header file	2021-03-26 17:03:08 +13:00
clk_scmi.c	clk: add clock driver for SCMI agents	2020-09-30 11:55:23 -04:00
clk_stm32f.c	clk: clk_stm32f: migrate trace to dev and log macro	2021-01-13 09:52:58 +01:00
clk_stm32h7.c	clk: clk_stm32h7: migrate trace to dev and log macro	2021-01-13 09:52:58 +01:00
clk_stm32mp1.c	clk: stm32mp1: add support of BSEC clock	2021-08-16 09:33:43 +02:00
clk_versaclock.c	clk: clk_versaclock: Add support for versaclock driver	2021-08-21 18:23:02 -04:00
clk_versal.c	clk: versal: Add support to enable clocks	2021-02-23 14:56:59 +01:00
clk_vexpress_osc.c	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
clk_zynq.c	Xilinx changes for v2021.04-rc3	2021-02-23 10:45:55 -05:00
clk_zynqmp.c	clk: zynqmp: Add support for enabling clock on lpd_lsbus	2021-07-26 09:18:45 +02:00
ics8n3qv01.c	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
Kconfig	clk: clk_versaclock: Add support for versaclock driver	2021-08-21 18:23:02 -04:00
Makefile	clk: clk_versaclock: Add support for versaclock driver	2021-08-21 18:23:02 -04:00
mpc83xx_clk.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
mpc83xx_clk.h	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00