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395 lines
11 KiB
C
395 lines
11 KiB
C
/*
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* ColdFire Internal Memory Map and Defines
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_H
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#define __IMMAP_H
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#ifdef CONFIG_M52277
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#include <asm/immap_5227x.h>
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#include <asm/m5227x.h>
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
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#define CFG_MCFRTC_BASE (MMAP_RTC)
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#ifdef CONFIG_LCD
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#define CFG_LCD_BASE (MMAP_LCD)
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#endif
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
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#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (6)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#ifdef CONFIG_MCFPIT
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#define CFG_UDELAY_BASE (MMAP_PIT0)
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#define CFG_PIT_BASE (MMAP_PIT1)
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#define CFG_PIT_PRESCALE (6)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#endif /* CONFIG_M52277 */
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#ifdef CONFIG_M5235
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#include <asm/immap_5235.h>
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#include <asm/m5235.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#ifdef CONFIG_MCFPIT
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#define CFG_UDELAY_BASE (MMAP_PIT0)
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#define CFG_PIT_BASE (MMAP_PIT1)
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#define CFG_PIT_PRESCALE (6)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#endif /* CONFIG_M5235 */
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#ifdef CONFIG_M5249
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#include <asm/immap_5249.h>
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#include <asm/m5249.h>
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC)
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#define CFG_NUM_IRQS (64)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
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#define CFG_TMRINTR_NO (31)
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#define CFG_TMRINTR_MASK (0x00000400)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5249 */
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#ifdef CONFIG_M5253
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#include <asm/immap_5253.h>
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#include <asm/m5249.h>
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#include <asm/m5253.h>
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC)
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#define CFG_NUM_IRQS (64)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
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#define CFG_TMRINTR_NO (27)
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#define CFG_TMRINTR_MASK (0x00000400)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5253 */
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#ifdef CONFIG_M5271
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#include <asm/immap_5271.h>
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#include <asm/m5271.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#endif /* CONFIG_M5271 */
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#ifdef CONFIG_M5272
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#include <asm/immap_5272.h>
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#include <asm/m5272.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC)
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#define CFG_NUM_IRQS (64)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_TMR0)
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#define CFG_TMR_BASE (MMAP_TMR3)
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#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
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#define CFG_TMRINTR_NO (INT_TMR3)
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#define CFG_TMRINTR_MASK (INT_ISR_INT24)
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#define CFG_TMRINTR_PEND (0)
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#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5272 */
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#ifdef CONFIG_M5275
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#include <asm/immap_5275.h>
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#include <asm/m5275.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC0)
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#define CFG_FEC1_IOBASE (MMAP_FEC1)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (192)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5275 */
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#ifdef CONFIG_M5282
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#include <asm/immap_5282.h>
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#include <asm/m5282.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5282 */
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#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
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#include <asm/immap_5329.h>
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#include <asm/m5329.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
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#define CFG_MCFRTC_BASE (MMAP_RTC)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
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#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (6)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#ifdef CONFIG_MCFPIT
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#define CFG_UDELAY_BASE (MMAP_PIT0)
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#define CFG_PIT_BASE (MMAP_PIT1)
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#define CFG_PIT_PRESCALE (6)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#endif /* CONFIG_M5329 && CONFIG_M5373 */
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#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
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#include <asm/immap_5445x.h>
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#include <asm/m5445x.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC0)
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#if defined(CONFIG_M54455EVB)
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#define CFG_FEC1_IOBASE (MMAP_FEC1)
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#endif
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
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#define CFG_MCFRTC_BASE (MMAP_RTC)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
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#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (6)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#ifdef CONFIG_MCFPIT
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#define CFG_UDELAY_BASE (MMAP_PIT0)
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#define CFG_PIT_BASE (MMAP_PIT1)
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#define CFG_PIT_PRESCALE (6)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#ifdef CONFIG_PCI
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#define CFG_PCI_BAR0 (CFG_MBAR)
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#define CFG_PCI_BAR5 (CFG_SDRAM_BASE)
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#define CFG_PCI_TBATR0 (CFG_MBAR)
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#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE)
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#endif
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#endif /* CONFIG_M54451 || CONFIG_M54455 */
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#ifdef CONFIG_M547x
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#include <asm/immap_547x_8x.h>
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#include <asm/m547x_8x.h>
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#ifdef CONFIG_FSLDMAFEC
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#define CFG_FEC0_IOBASE (MMAP_FEC0)
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#define CFG_FEC1_IOBASE (MMAP_FEC1)
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#define FEC0_RX_TASK 0
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#define FEC0_TX_TASK 1
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#define FEC0_RX_PRIORITY 6
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#define FEC0_TX_PRIORITY 7
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#define FEC0_RX_INIT 16
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#define FEC0_TX_INIT 17
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#define FEC1_RX_TASK 2
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#define FEC1_TX_TASK 3
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#define FEC1_RX_PRIORITY 6
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#define FEC1_TX_PRIORITY 7
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#define FEC1_RX_INIT 30
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#define FEC1_TX_INIT 31
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#endif
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100))
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#ifdef CONFIG_SLTTMR
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#define CFG_UDELAY_BASE (MMAP_SLT1)
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#define CFG_TMR_BASE (MMAP_SLT0)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
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#define CFG_TMRINTR_NO (INT0_HI_SLT0)
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#define CFG_TMRINTR_MASK (INTC_IPRH_INT54)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E)
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#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#ifdef CONFIG_PCI
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#define CFG_PCI_BAR0 (0x40000000)
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#define CFG_PCI_BAR1 (CFG_SDRAM_BASE)
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#define CFG_PCI_TBATR0 (CFG_MBAR)
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#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE)
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#endif
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#endif /* CONFIG_M547x */
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#ifdef CONFIG_M548x
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#include <asm/immap_547x_8x.h>
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#include <asm/m547x_8x.h>
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#ifdef CONFIG_FSLDMAFEC
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#define CFG_FEC0_IOBASE (MMAP_FEC0)
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#define CFG_FEC1_IOBASE (MMAP_FEC1)
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#define FEC0_RX_TASK 0
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#define FEC0_TX_TASK 1
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#define FEC0_RX_PRIORITY 6
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#define FEC0_TX_PRIORITY 7
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#define FEC0_RX_INIT 16
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#define FEC0_TX_INIT 17
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#define FEC1_RX_TASK 2
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#define FEC1_TX_TASK 3
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#define FEC1_RX_PRIORITY 6
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#define FEC1_TX_PRIORITY 7
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#define FEC1_RX_INIT 30
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#define FEC1_TX_INIT 31
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#endif
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100))
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/* Timer */
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#ifdef CONFIG_SLTTMR
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#define CFG_UDELAY_BASE (MMAP_SLT1)
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#define CFG_TMR_BASE (MMAP_SLT0)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
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#define CFG_TMRINTR_NO (INT0_HI_SLT0)
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#define CFG_TMRINTR_MASK (INTC_IPRH_INT54)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E)
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#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#ifdef CONFIG_PCI
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#define CFG_PCI_BAR0 (CFG_MBAR)
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#define CFG_PCI_BAR1 (CFG_SDRAM_BASE)
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#define CFG_PCI_TBATR0 (CFG_MBAR)
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#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE)
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#endif
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#endif /* CONFIG_M548x */
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#endif /* __IMMAP_H */
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