mirror of
https://github.com/AsahiLinux/u-boot
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297 lines
11 KiB
C
297 lines
11 KiB
C
/*
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* (C) Copyright 2002
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* board/config_CPCI440.h - configuration for esd CPCI-440 board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_CPCI440 1 /* Board is ebony */
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#define CONFIG_440GP 1 /* Specifc GP support */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#undef CFG_DRAM_TEST /* Disable-takes long time! */
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#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
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#if 1
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#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
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#else
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#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */
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#endif
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
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#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
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#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */
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#define CONFIG_BAUDRATE 9600
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
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* The DS1743 code assumes this condition (i.e. -- it assumes the base
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* address for the RTC registers is:
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*
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* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
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*
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*----------------------------------------------------------------------*/
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#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#if 1 /* test-only */
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
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#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#undef CFG_FLASH_BASE
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#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/
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#else /* test-only */
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#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
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#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#endif
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#if 0 /* test-only */
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#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
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#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
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#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
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#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
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#define CFG_ENV_ADDR \
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(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
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#else
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#if 0 /* test-only */
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
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/* total size of a CAT24WC16 is 2048 bytes */
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#else
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#endif
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_BAUDRATE 9600
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#if 0 /* test-only */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_IRQ | \
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CFG_CMD_I2C | \
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CFG_CMD_KGDB | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE | \
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CFG_CMD_BEDBUG | \
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CFG_CMD_ELF )
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#else
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_IRQ | \
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CFG_CMD_ELF | \
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CFG_CMD_DATE | \
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CFG_CMD_I2C | \
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CFG_CMD_EEPROM )
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/* test-only: support fehlt bisher... */
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/* CFG_CMD_IDE | \*/
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/* CFG_CMD_PCI | \*/
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#endif
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#if 0 /* test-only */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#if 0
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/* Configuration Port location */
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#define CONFIG_PORT_ADDR 0xF0000500
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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*/
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#define SPD_EEPROM_ADDRESS 0x50
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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