mirror of
https://github.com/AsahiLinux/u-boot
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293 lines
6.1 KiB
C
293 lines
6.1 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_HARD_I2C
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#include <command.h>
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#include <i2c.h> /* Functional interface */
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#include <asm/io.h>
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#include <asm/fsl_i2c.h> /* HW definitions */
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#define I2C_TIMEOUT (CFG_HZ / 4)
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#define I2C_READ_BIT 1
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#define I2C_WRITE_BIT 0
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 0. This is necessary because the DDR initialization
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* runs from ROM, and we can't switch buses because we can't modify
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* the global variables.
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*/
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#ifdef CFG_SPD_BUS_NUM
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static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
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#else
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static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
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#endif
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static volatile struct fsl_i2c *i2c_dev[2] = {
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(struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
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#ifdef CFG_I2C2_OFFSET
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(struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
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#endif
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};
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void
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i2c_init(int speed, int slaveadd)
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{
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volatile struct fsl_i2c *dev;
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dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
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writeb(0, &dev->cr); /* stop I2C controller */
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writeb(0x3F, &dev->fdr); /* set bus speed */
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writeb(0x3F, &dev->dfsrr); /* set default filter */
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writeb(slaveadd << 1, &dev->adr); /* write slave address */
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writeb(0x0, &dev->sr); /* clear status register */
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writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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#ifdef CFG_I2C2_OFFSET
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dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
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writeb(0, &dev->cr); /* stop I2C controller */
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writeb(0x3F, &dev->fdr); /* set bus speed */
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writeb(0x3F, &dev->dfsrr); /* set default filter */
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writeb(slaveadd, &dev->adr); /* write slave address */
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writeb(0x0, &dev->sr); /* clear status register */
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writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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#endif /* CFG_I2C2_OFFSET */
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}
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static __inline__ int
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i2c_wait4bus(void)
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{
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ulong timeval = get_timer(0);
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while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
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if (get_timer(timeval) > I2C_TIMEOUT) {
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return -1;
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}
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}
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return 0;
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}
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static __inline__ int
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i2c_wait(int write)
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{
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u32 csr;
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ulong timeval = get_timer(0);
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do {
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csr = readb(&i2c_dev[i2c_bus_num]->sr);
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if (!(csr & I2C_SR_MIF))
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continue;
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writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
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if (csr & I2C_SR_MAL) {
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debug("i2c_wait: MAL\n");
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return -1;
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}
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if (!(csr & I2C_SR_MCF)) {
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debug("i2c_wait: unfinished\n");
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return -1;
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}
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if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
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debug("i2c_wait: No RXACK\n");
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return -1;
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}
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return 0;
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} while (get_timer (timeval) < I2C_TIMEOUT);
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debug("i2c_wait: timed out\n");
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return -1;
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}
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static __inline__ int
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i2c_write_addr (u8 dev, u8 dir, int rsta)
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{
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
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| (rsta ? I2C_CR_RSTA : 0),
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&i2c_dev[i2c_bus_num]->cr);
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writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
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if (i2c_wait(I2C_WRITE_BIT) < 0)
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return 0;
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return 1;
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}
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static __inline__ int
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__i2c_write(u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
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&i2c_dev[i2c_bus_num]->cr);
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for (i = 0; i < length; i++) {
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writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
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if (i2c_wait(I2C_WRITE_BIT) < 0)
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break;
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}
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return i;
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}
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static __inline__ int
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__i2c_read(u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
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&i2c_dev[i2c_bus_num]->cr);
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/* dummy read */
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readb(&i2c_dev[i2c_bus_num]->dr);
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for (i = 0; i < length; i++) {
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if (i2c_wait(I2C_READ_BIT) < 0)
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break;
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/* Generate ack on last next to last byte */
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if (i == length - 2)
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
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&i2c_dev[i2c_bus_num]->cr);
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/* Generate stop on last byte */
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if (i == length - 1)
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writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
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data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
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}
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return i;
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}
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int
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i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = 0;
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus() >= 0
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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&& __i2c_write(&a[4 - alen], alen) == alen
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&& i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) {
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i = __i2c_read(data, length);
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}
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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if (i == length)
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return 0;
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return -1;
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}
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int
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i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = 0;
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus() >= 0
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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&& __i2c_write(&a[4 - alen], alen) == alen) {
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i = __i2c_write(data, length);
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}
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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if (i == length)
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return 0;
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return -1;
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}
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int
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i2c_probe(uchar chip)
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{
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int tmp;
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/*
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* Try to read the first location of the chip. The underlying
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* driver doesn't appear to support sending just the chip address
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* and looking for an <ACK> back.
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*/
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udelay(10000);
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return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
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}
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uchar
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i2c_reg_read(uchar i2c_addr, uchar reg)
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{
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uchar buf[1];
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i2c_read(i2c_addr, reg, 1, buf, 1);
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return buf[0];
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}
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void
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i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
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{
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i2c_write(i2c_addr, reg, 1, &val, 1);
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}
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int i2c_set_bus_num(unsigned int bus)
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{
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#ifdef CFG_I2C2_OFFSET
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if (bus > 1) {
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#else
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if (bus > 0) {
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#endif
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return -1;
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}
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i2c_bus_num = bus;
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return 0;
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}
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int i2c_set_bus_speed(unsigned int speed)
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{
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return -1;
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}
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unsigned int i2c_get_bus_num(void)
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{
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return i2c_bus_num;
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}
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unsigned int i2c_get_bus_speed(void)
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{
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return 0;
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}
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#endif /* CONFIG_HARD_I2C */
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#endif /* CONFIG_FSL_I2C */
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