mirror of
https://github.com/AsahiLinux/u-boot
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283 lines
7.4 KiB
C
283 lines
7.4 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#if defined(CFG_RTCSC) || defined(CFG_RMDS)
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
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void cpm_load_patch (volatile immap_t * immr);
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#endif
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (volatile immap_t * immr)
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{
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#ifndef CONFIG_MBX
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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# ifdef CFG_PLPRCR
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ulong mfmask;
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# endif
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#endif
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ulong reg;
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/* SYPCR - contains watchdog control (11-9) */
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immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
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#if defined(CONFIG_WATCHDOG)
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reset_8xx_watchdog (immr);
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#endif /* CONFIG_WATCHDOG */
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/* SIUMCR - contains debug pin configuration (11-6) */
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#ifndef CONFIG_SVM_SC8xx
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immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
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#else
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immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
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#endif
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/* initialize timebase status and control register (11-26) */
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/* unlock TBSCRK */
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immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
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immr->im_sit.sit_tbscr = CFG_TBSCR;
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/* initialize the PIT (11-31) */
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immr->im_sitk.sitk_piscrk = KAPWR_KEY;
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immr->im_sit.sit_piscr = CFG_PISCR;
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/* System integration timers. Don't change EBDF! (15-27) */
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immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
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reg = immr->im_clkrst.car_sccr;
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reg &= SCCR_MASK;
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reg |= CFG_SCCR;
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immr->im_clkrst.car_sccr = reg;
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/* PLL (CPU clock) settings (15-30) */
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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#ifndef CONFIG_MBX /* MBX board does things different */
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/* If CFG_PLPRCR (set in the various *_config.h files) tries to
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* set the MF field, then just copy CFG_PLPRCR over car_plprcr,
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* otherwise OR in CFG_PLPRCR so we do not change the current MF
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* field value.
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*
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* For newer (starting MPC866) chips PLPRCR layout is different.
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*/
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#ifdef CFG_PLPRCR
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if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
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mfmask = PLPRCR_MFACT_MSK;
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else
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mfmask = PLPRCR_MF_MSK;
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if ((CFG_PLPRCR & mfmask) != 0)
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reg = CFG_PLPRCR; /* reset control bits */
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else {
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reg = immr->im_clkrst.car_plprcr;
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reg &= mfmask; /* isolate MF-related fields */
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reg |= CFG_PLPRCR; /* reset control bits */
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}
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immr->im_clkrst.car_plprcr = reg;
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#endif
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/*
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* Memory Controller:
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*/
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/* perform BR0 reset that MPC850 Rev. A can't guarantee */
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reg = memctl->memc_br0;
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reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
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reg |= BR_V; /* then add just the "Bank Valid" bit */
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memctl->memc_br0 = reg;
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/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
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* preliminary addresses - these have to be modified later
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* when FLASH size has been determined
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*
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* Depending on the size of the memory region defined by
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* CFG_OR0_REMAP some boards (wide address mask) allow to map the
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* CFG_MONITOR_BASE, while others (narrower address mask) can't
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* map CFG_MONITOR_BASE.
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*
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* For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
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* 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
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*
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* If BR0 wasn't loaded with address base 0xff000000, then BR0's
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* base address remains as 0x00000000. However, the address mask
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* have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
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* into the Bank0.
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*
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* This is why CONFIG_IVMS8 and similar boards must load BR0 with
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* CFG_BR0_PRELIM in advance.
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*
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* [Thanks to Michael Liao for this explanation.
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* I owe him a free beer. - wd]
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*/
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#if defined(CONFIG_GTH) || \
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defined(CONFIG_HERMES) || \
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defined(CONFIG_ICU862) || \
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defined(CONFIG_IP860) || \
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defined(CONFIG_IVML24) || \
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defined(CONFIG_IVMS8) || \
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defined(CONFIG_LWMON) || \
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defined(CONFIG_MHPC) || \
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defined(CONFIG_PCU_E) || \
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defined(CONFIG_R360MPI) || \
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defined(CONFIG_RMU) || \
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defined(CONFIG_RPXCLASSIC) || \
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defined(CONFIG_RPXLITE) || \
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defined(CONFIG_SPC1920) || \
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defined(CONFIG_SPD823TS)
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memctl->memc_br0 = CFG_BR0_PRELIM;
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#endif
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#if defined(CFG_OR0_REMAP)
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memctl->memc_or0 = CFG_OR0_REMAP;
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#endif
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#if defined(CFG_OR1_REMAP)
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memctl->memc_or1 = CFG_OR1_REMAP;
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#endif
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#if defined(CFG_OR5_REMAP)
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memctl->memc_or5 = CFG_OR5_REMAP;
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#endif
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/* now restrict to preliminary range */
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memctl->memc_br0 = CFG_BR0_PRELIM;
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memctl->memc_or0 = CFG_OR0_PRELIM;
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#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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#endif
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#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
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memctl->memc_br0 = 0;
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#endif
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#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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#endif
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#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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#endif
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#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
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memctl->memc_or4 = CFG_OR4_PRELIM;
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memctl->memc_br4 = CFG_BR4_PRELIM;
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#endif
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#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
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memctl->memc_or5 = CFG_OR5_PRELIM;
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memctl->memc_br5 = CFG_BR5_PRELIM;
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#endif
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#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
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memctl->memc_or6 = CFG_OR6_PRELIM;
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memctl->memc_br6 = CFG_BR6_PRELIM;
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#endif
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#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
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memctl->memc_or7 = CFG_OR7_PRELIM;
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memctl->memc_br7 = CFG_BR7_PRELIM;
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#endif
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#endif /* ! CONFIG_MBX */
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/*
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* Reset CPM
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*/
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immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
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do { /* Spin until command processed */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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#ifdef CONFIG_MBX
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/*
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* on the MBX, things are a little bit different:
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* - we need to read the VPD to get board information
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* - the plprcr is set up dynamically
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* - the memory controller is set up dynamically
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*/
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mbx_init ();
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#endif /* CONFIG_MBX */
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#ifdef CONFIG_RPXCLASSIC
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rpxclassic_init ();
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#endif
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#if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM)
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rpxlite_init ();
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#endif
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#ifdef CFG_RCCR /* must be done before cpm_load_patch() */
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/* write config value */
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immr->im_cpm.cp_rccr = CFG_RCCR;
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#endif
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#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
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cpm_load_patch (immr); /* load mpc8xx microcode patch */
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#endif
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r (void)
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{
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#if defined(CFG_RTCSC) || defined(CFG_RMDS)
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bd_t *bd = gd->bd;
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volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
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#endif
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#ifdef CFG_RTCSC
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/* Unlock RTSC register */
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immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
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/* write config value */
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immr->im_sit.sit_rtcsc = CFG_RTCSC;
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#endif
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#ifdef CFG_RMDS
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/* write config value */
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immr->im_cpm.cp_rmds = CFG_RMDS;
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#endif
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return (0);
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}
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