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68049a082b
I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
172 lines
5.8 KiB
C
172 lines
5.8 KiB
C
/*
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* NVIDIA Tegra I2C controller
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*
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* Copyright 2010-2011 NVIDIA Corporation
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA_I2C_H_
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#define _TEGRA_I2C_H_
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#include <asm/types.h>
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enum {
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I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
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I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
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};
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enum i2c_transaction_flags {
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I2C_IS_WRITE = 0x1, /* for I2C write operation */
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I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
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I2C_USE_REPEATED_START = 0x4, /* for repeat start */
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I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
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I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
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I2C_NO_STOP = 0x20,
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};
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/* Contians the I2C transaction details */
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struct i2c_trans_info {
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/* flags to indicate the transaction details */
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enum i2c_transaction_flags flags;
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u32 address; /* I2C slave device address */
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u32 num_bytes; /* number of bytes to be transferred */
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/*
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* Send/receive buffer. For the I2C send operation this buffer should
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* be filled with the data to be sent to the slave device. For the I2C
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* receive operation this buffer is filled with the data received from
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* the slave device.
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*/
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u8 *buf;
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int is_10bit_address;
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};
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struct i2c_control {
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u32 tx_fifo;
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u32 rx_fifo;
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u32 packet_status;
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u32 fifo_control;
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u32 fifo_status;
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u32 int_mask;
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u32 int_status;
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};
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struct dvc_ctlr {
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u32 ctrl1; /* 00: DVC_CTRL_REG1 */
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u32 ctrl2; /* 04: DVC_CTRL_REG2 */
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u32 ctrl3; /* 08: DVC_CTRL_REG3 */
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u32 status; /* 0C: DVC_STATUS_REG */
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u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
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u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
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u32 reserved_0[2]; /* 18: */
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u32 req; /* 20: DVC_REQ_REGISTER */
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u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
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u32 reserved_1[6]; /* 28: */
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u32 cnfg; /* 40: DVC_I2C_CNFG */
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u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
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u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
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u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
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u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
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u32 reserved_2[2]; /* 54: */
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u32 i2c_status; /* 5C: DVC_I2C_STATUS */
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struct i2c_control control; /* 60 ~ 78 */
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};
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struct i2c_ctlr {
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u32 cnfg; /* 00: I2C_I2C_CNFG */
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u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
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u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
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u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
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u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
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u32 reserved_0[2]; /* 14: */
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u32 status; /* 1C: I2C_I2C_STATUS */
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u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
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u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
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u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
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u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
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u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
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u32 reserved_1[2]; /* 34: */
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u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
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u32 reserved_2[4]; /* 40: */
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struct i2c_control control; /* 50 ~ 68 */
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u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
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};
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/* bit fields definitions for IO Packet Header 1 format */
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#define PKT_HDR1_PROTOCOL_SHIFT 4
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#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
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#define PKT_HDR1_CTLR_ID_SHIFT 12
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#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
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#define PKT_HDR1_PKT_ID_SHIFT 16
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#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
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#define PROTOCOL_TYPE_I2C 1
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/* bit fields definitions for IO Packet Header 2 format */
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#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
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#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
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/* bit fields definitions for IO Packet Header 3 format */
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#define PKT_HDR3_READ_MODE_SHIFT 19
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#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
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#define PKT_HDR3_REPEAT_START_SHIFT 16
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#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT)
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#define PKT_HDR3_SLAVE_ADDR_SHIFT 0
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#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
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#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
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#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
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(1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
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/* I2C_CNFG */
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#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
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#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
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#define I2C_CNFG_PACKET_MODE_SHIFT 10
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#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
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/* I2C_SL_CNFG */
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#define I2C_SL_CNFG_NEWSL_SHIFT 2
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#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
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/* I2C_FIFO_STATUS */
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#define TX_FIFO_FULL_CNT_SHIFT 0
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#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
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#define TX_FIFO_EMPTY_CNT_SHIFT 4
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#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
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/* I2C_INTERRUPT_STATUS */
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#define I2C_INT_XFER_COMPLETE_SHIFT 7
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#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
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#define I2C_INT_NO_ACK_SHIFT 3
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#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
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#define I2C_INT_ARBITRATION_LOST_SHIFT 2
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#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
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/* I2C_CLK_DIVISOR_REGISTER */
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#define CLK_DIV_STD_FAST_MODE 0x19
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#define CLK_DIV_HS_MODE 1
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#define CLK_MULT_STD_FAST_MODE 8
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/**
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* Returns the bus number of the DVC controller
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*
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* @return number of bus, or -1 if there is no DVC active
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*/
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int tegra_i2c_get_dvc_bus_num(void);
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#endif /* _TEGRA_I2C_H_ */
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