mirror of
https://github.com/AsahiLinux/u-boot
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881284b36a
This erratum is reported to cause problems on these processors [1-3]. The problem is usually with the clocking, which is supposed to be configured by the RCW [4]. However, if it is not set, or if the default clocking is not correct, then this erratum will cause an SError. However, according to Ran Wang in [1]: " ... this erratum is used to pass USB compliance test only, you could disable this workaround on your board if you don't any USB issue on normal use case, I think it's fine." So just disable this erratum by default for these processors. [1] https://lore.kernel.org/all/761ddd61-05c1-d9b8-ac90-b8f425afde6c@denx.de/ [2] https://community.nxp.com/t5/Layerscape/LS1046A-U-BOOT-HALT-AT-ERRATUM-A0090078/m-p/742993 [3] https://community.nxp.com/t5/QorIQ/Why-does-the-LS1043A-U-Boot-hang-at-code-that-fixes-erratum/m-p/644412 [4] https://source.codeaurora.org/external/qoriq/qoriq-components/rcw/tree/ls1046ardb/usb_phy_freq.rcw Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Ran Wang <ran.wang_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
105 lines
2.3 KiB
Text
105 lines
2.3 KiB
Text
config ARCH_LS1021A
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bool
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select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008997 if USB
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select SYS_FSL_ERRATUM_A009008 if USB
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009798 if USB
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_I2C_MXC
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imply CMD_PCI
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imply SCSI
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imply SCSI_AHCI
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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config LS1_DEEP_SLEEP
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bool "Deep sleep"
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config MAX_CPUS
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int "Maximum number of CPUs permitted for LS102xA"
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default 2
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config NXP_ESBC
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bool "NXP_ESBC"
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help
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Enable Freescale Secure Boot feature. Normally selected
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by defconfig. If unsure, do not change.
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config SYS_CCI400_OFFSET
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hex "Offset for CCI400 base"
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depends on SYS_FSL_HAS_CCI400
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default 0x180000
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help
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Offset for CCI400 base.
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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config SYS_FSL_ERRATUM_A008850
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bool
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help
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Workaround for DDR erratum A008850
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config SYS_FSL_ERRATUM_A008997
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bool
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help
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Workaround for USB PHY erratum A008997
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config SYS_FSL_ERRATUM_A009007
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bool
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help
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Workaround for USB PHY erratum A009007
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config SYS_FSL_ERRATUM_A009008
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bool
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help
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Workaround for USB PHY erratum A009008
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config SYS_FSL_ERRATUM_A009798
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bool
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help
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Workaround for USB PHY erratum A009798
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_HAS_CCI400
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bool
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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default 8
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config SYS_FSL_ERRATUM_A008407
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bool
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endmenu
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