mirror of
https://github.com/AsahiLinux/u-boot
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238 lines
7.2 KiB
C
Executable file
238 lines
7.2 KiB
C
Executable file
/*
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* (C) Copyright 2005-2007
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* Samsung Electronics,
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Configuration settings for the 2420 Samsung Apollon board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP2420 1 /* which is in a 2420 */
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#define CONFIG_OMAP2420_APOLLON 1
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#define CONFIG_APOLLON 1
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#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
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/* Clock config to target*/
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#define PRCM_CONFIG_I 1
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/* #define PRCM_CONFIG_II 1 */
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/* Boot method */
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/* uncomment if you use NOR boot */
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/* #define CFG_NOR_BOOT 1 */
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/* uncomment if you use NOR on CS3 */
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/* #define CFG_USE_NOR 1 */
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#ifdef CFG_NOR_BOOT
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#undef CFG_USE_NOR
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#define CFG_USE_NOR 1
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#endif
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#include <asm/arch/omap2420.h> /* get chip and board defs */
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#define V_SCLK 12000000
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/* input clock of PLL */
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/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
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#define CONFIG_SYS_CLK_FREQ V_SCLK
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
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#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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/*
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* SMC91c96 Etherent
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*/
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#define CONFIG_DRIVER_LAN91C96
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#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
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#define CONFIG_LAN91C96_EXT_PHY
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE (-4)
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#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
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#define CFG_NS16550_COM1 OMAP2420_UART1
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* UART1 on H4 */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 100000
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#define CFG_I2C_SLAVE 1
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#define CONFIG_DRIVER_OMAP24XX_I2C
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_ONENAND
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#undef CONFIG_CMD_AUTOSCRIPT
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#ifndef CFG_USE_NOR
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# undef CONFIG_CMD_FLASH
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# undef CONFIG_CMD_IMLS
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#endif
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.116.25
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#define CONFIG_SERVERIP 192.168.116.1
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_ETHADDR 00:0E:99:00:24:20
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#ifdef CONFIG_APOLLON_PLUS
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# define CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
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#else
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# define CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"Image=tftp 0x80008000 Image; go 0x80008000\0" \
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"zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
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"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
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"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
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"xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
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"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
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"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
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"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
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"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
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"onesyncboot=run syncmode oneboot\0" \
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"bootcmd=run uboot\0"
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/*
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* Miscellaneous configurable options
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*/
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#define V_PROMPT "Apollon # "
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT V_PROMPT
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
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#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
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/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
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* or by 32KHz clk, or from external sig. This rate is divided by a local
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* divisor.
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*/
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#define V_PVT 7 /* use with 12MHz/128 */
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#define CFG_TIMERBASE OMAP2420_GPT2
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#define CFG_PVT V_PVT /* 2^(pvt+1) */
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#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE SZ_128K /* regular stack */
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#ifdef CONFIG_USE_IRQ
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# define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
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# define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE SZ_128M
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#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#ifdef CFG_USE_NOR
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/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
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# define CFG_FLASH_BASE 0x18000000
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# define CFG_MAX_FLASH_BANKS 1
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# define CFG_MAX_FLASH_SECT 1024
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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# define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
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# define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
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# define CFG_FLASH_PROTECTION 1 /* Use h/w sector protection*/
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#else /* !CFG_USE_NOR */
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# define CFG_NO_FLASH 1
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#endif /* CFG_USE_NOR */
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/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
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#define CFG_ONENAND_BASE 0x00000000
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#define CFG_ENV_IS_IN_ONENAND 1
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#define CFG_ENV_ADDR 0x00020000
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#endif /* __CONFIG_H */
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