mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
88 lines
2.2 KiB
Text
88 lines
2.2 KiB
Text
CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0xFFF40000
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CONFIG_SYS_MALLOC_LEN=0x100000
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x100000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P5040DS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
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CONFIG_DYNAMIC_SYS_CLK_FREQ=y
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CONFIG_RAMBOOT_PBL=y
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CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
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CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_ID_EEPROM=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_MP=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_DM=y
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CONFIG_FSL_CAAM=y
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CONFIG_DDR_ECC=y
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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CONFIG_SYS_BR0_PRELIM_BOOL=y
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CONFIG_SYS_BR0_PRELIM=0xE8001001
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CONFIG_SYS_OR0_PRELIM=0xF8000F85
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CONFIG_SYS_BR1_PRELIM_BOOL=y
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CONFIG_SYS_BR1_PRELIM=0xE0001001
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CONFIG_SYS_OR1_PRELIM=0xF8000FF7
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CONFIG_SYS_BR3_PRELIM_BOOL=y
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CONFIG_SYS_BR3_PRELIM=0xFFDF0801
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CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
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CONFIG_DM_I2C=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_FSL=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=10000000
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_FMAN_ENET=y
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CONFIG_SYS_FMAN_FW_ADDR=0x110000
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CONFIG_MII=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_ESPI=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_FSL=y
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CONFIG_USB_STORAGE=y
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CONFIG_ADDR_MAP=y
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CONFIG_SYS_NUM_ADDR_MAP=64
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