mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
1dff9d0f54
Add AX88772B ID together with two fixes needed to make this work. 1. The packet length check has to be adjusted, as all ASIX chips only use 11 bits to indicate the length. AX88772B uses the other bits to indicate unrelated things, which cause the check to fail. This fix is based on a fix for the Linux kernel by Marek Vasut. Linux upstream commit: bca0beb9363f8487ac902931a50eb00180a2d14a 2. AX88772B provides several bulk endpoints. Only the first IN/OUT endpoints work in the default configuration. So stop enumeration after we found them to avoid overwriting the endpoint config with a non-working one. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
722 lines
18 KiB
C
722 lines
18 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <usb.h>
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#include <linux/mii.h>
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#include "usb_ether.h"
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#include <malloc.h>
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/* ASIX AX8817X based USB 2.0 Ethernet Devices */
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#define AX_CMD_SET_SW_MII 0x06
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#define AX_CMD_READ_MII_REG 0x07
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#define AX_CMD_WRITE_MII_REG 0x08
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#define AX_CMD_SET_HW_MII 0x0a
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#define AX_CMD_READ_EEPROM 0x0b
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#define AX_CMD_READ_RX_CTL 0x0f
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#define AX_CMD_WRITE_RX_CTL 0x10
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#define AX_CMD_WRITE_IPG0 0x12
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#define AX_CMD_READ_NODE_ID 0x13
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#define AX_CMD_WRITE_NODE_ID 0x14
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#define AX_CMD_READ_PHY_ID 0x19
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#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
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#define AX_CMD_WRITE_GPIOS 0x1f
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#define AX_CMD_SW_RESET 0x20
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#define AX_CMD_SW_PHY_SELECT 0x22
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#define AX_SWRESET_CLEAR 0x00
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#define AX_SWRESET_PRTE 0x04
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#define AX_SWRESET_PRL 0x08
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#define AX_SWRESET_IPRL 0x20
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#define AX_SWRESET_IPPD 0x40
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#define AX88772_IPG0_DEFAULT 0x15
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#define AX88772_IPG1_DEFAULT 0x0c
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#define AX88772_IPG2_DEFAULT 0x12
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/* AX88772 & AX88178 Medium Mode Register */
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#define AX_MEDIUM_PF 0x0080
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#define AX_MEDIUM_JFE 0x0040
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#define AX_MEDIUM_TFC 0x0020
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#define AX_MEDIUM_RFC 0x0010
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#define AX_MEDIUM_ENCK 0x0008
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#define AX_MEDIUM_AC 0x0004
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#define AX_MEDIUM_FD 0x0002
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#define AX_MEDIUM_GM 0x0001
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#define AX_MEDIUM_SM 0x1000
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#define AX_MEDIUM_SBP 0x0800
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#define AX_MEDIUM_PS 0x0200
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#define AX_MEDIUM_RE 0x0100
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#define AX88178_MEDIUM_DEFAULT \
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(AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
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AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
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AX_MEDIUM_RE)
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#define AX88772_MEDIUM_DEFAULT \
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(AX_MEDIUM_FD | AX_MEDIUM_RFC | \
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AX_MEDIUM_TFC | AX_MEDIUM_PS | \
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AX_MEDIUM_AC | AX_MEDIUM_RE)
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/* AX88772 & AX88178 RX_CTL values */
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#define AX_RX_CTL_SO 0x0080
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#define AX_RX_CTL_AB 0x0008
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#define AX_DEFAULT_RX_CTL \
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(AX_RX_CTL_SO | AX_RX_CTL_AB)
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/* GPIO 2 toggles */
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#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
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#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
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#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
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/* local defines */
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#define ASIX_BASE_NAME "asx"
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#define USB_CTRL_SET_TIMEOUT 5000
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#define USB_CTRL_GET_TIMEOUT 5000
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#define USB_BULK_SEND_TIMEOUT 5000
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#define USB_BULK_RECV_TIMEOUT 5000
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#define AX_RX_URB_SIZE 2048
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#define PHY_CONNECT_TIMEOUT 5000
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/* asix_flags defines */
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#define FLAG_NONE 0
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#define FLAG_TYPE_AX88172 (1U << 0)
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#define FLAG_TYPE_AX88772 (1U << 1)
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#define FLAG_TYPE_AX88772B (1U << 2)
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#define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
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/* local vars */
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static int curr_eth_dev; /* index for name of next device detected */
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/* driver private */
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struct asix_private {
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int flags;
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};
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/*
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* Asix infrastructure commands
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*/
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static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
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u16 size, void *data)
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{
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int len;
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debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
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"size=%d\n", cmd, value, index, size);
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len = usb_control_msg(
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dev->pusb_dev,
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usb_sndctrlpipe(dev->pusb_dev, 0),
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cmd,
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USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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value,
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index,
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data,
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size,
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USB_CTRL_SET_TIMEOUT);
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return len == size ? 0 : -1;
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}
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static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
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u16 size, void *data)
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{
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int len;
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debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
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cmd, value, index, size);
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len = usb_control_msg(
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dev->pusb_dev,
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usb_rcvctrlpipe(dev->pusb_dev, 0),
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cmd,
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USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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value,
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index,
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data,
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size,
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USB_CTRL_GET_TIMEOUT);
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return len == size ? 0 : -1;
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}
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static inline int asix_set_sw_mii(struct ueth_data *dev)
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{
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int ret;
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ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
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if (ret < 0)
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debug("Failed to enable software MII access\n");
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return ret;
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}
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static inline int asix_set_hw_mii(struct ueth_data *dev)
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{
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int ret;
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ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
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if (ret < 0)
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debug("Failed to enable hardware MII access\n");
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return ret;
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}
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static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
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{
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ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
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asix_set_sw_mii(dev);
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asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
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asix_set_hw_mii(dev);
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debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
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phy_id, loc, le16_to_cpu(*res));
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return le16_to_cpu(*res);
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}
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static void
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asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
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{
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ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
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*res = cpu_to_le16(val);
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debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
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phy_id, loc, val);
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asix_set_sw_mii(dev);
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asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
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asix_set_hw_mii(dev);
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}
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/*
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* Asix "high level" commands
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*/
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static int asix_sw_reset(struct ueth_data *dev, u8 flags)
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{
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int ret;
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ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
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if (ret < 0)
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debug("Failed to send software reset: %02x\n", ret);
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else
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udelay(150 * 1000);
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return ret;
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}
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static inline int asix_get_phy_addr(struct ueth_data *dev)
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{
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ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
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int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
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debug("asix_get_phy_addr()\n");
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if (ret < 0) {
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debug("Error reading PHYID register: %02x\n", ret);
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goto out;
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}
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debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
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ret = buf[1];
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out:
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return ret;
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}
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static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
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{
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int ret;
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debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
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0, 0, NULL);
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if (ret < 0) {
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debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
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mode, ret);
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}
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return ret;
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}
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static u16 asix_read_rx_ctl(struct ueth_data *dev)
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{
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ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
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int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
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if (ret < 0)
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debug("Error reading RX_CTL register: %02x\n", ret);
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else
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ret = le16_to_cpu(*v);
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return ret;
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}
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static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
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{
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int ret;
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debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
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if (ret < 0) {
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debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
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mode, ret);
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}
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return ret;
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}
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static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
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{
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int ret;
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debug("asix_write_gpio() - value = 0x%04x\n", value);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
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if (ret < 0) {
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debug("Failed to write GPIO value 0x%04x: %02x\n",
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value, ret);
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}
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if (sleep)
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udelay(sleep * 1000);
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return ret;
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}
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static int asix_write_hwaddr(struct eth_device *eth)
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{
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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int ret;
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
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memcpy(buf, eth->enetaddr, ETH_ALEN);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
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if (ret < 0)
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debug("Failed to set MAC address: %02x\n", ret);
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return ret;
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}
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/*
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* mii commands
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*/
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/*
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* mii_nway_restart - restart NWay (autonegotiation) for this interface
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*
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* Returns 0 on success, negative on error.
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*/
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static int mii_nway_restart(struct ueth_data *dev)
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{
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int bmcr;
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int r = -1;
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/* if autoneg is off, it's an error */
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bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
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if (bmcr & BMCR_ANENABLE) {
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bmcr |= BMCR_ANRESTART;
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asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
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r = 0;
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}
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return r;
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}
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static int asix_read_mac(struct eth_device *eth)
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{
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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struct asix_private *priv = (struct asix_private *)dev->dev_priv;
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int i;
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
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if (priv->flags & FLAG_EEPROM_MAC) {
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for (i = 0; i < (ETH_ALEN >> 1); i++) {
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if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
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0x04 + i, 0, 2, buf) < 0) {
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debug("Failed to read SROM address 04h.\n");
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return -1;
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}
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memcpy((eth->enetaddr + i * 2), buf, 2);
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}
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} else {
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if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
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< 0) {
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debug("Failed to read MAC address.\n");
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return -1;
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}
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memcpy(eth->enetaddr, buf, ETH_ALEN);
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}
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return 0;
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}
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static int asix_basic_reset(struct ueth_data *dev)
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{
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int embd_phy;
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u16 rx_ctl;
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if (asix_write_gpio(dev,
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AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
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return -1;
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/* 0x10 is the phy id of the embedded 10/100 ethernet phy */
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embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
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if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
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embd_phy, 0, 0, NULL) < 0) {
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debug("Select PHY #1 failed\n");
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return -1;
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}
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if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
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return -1;
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if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
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return -1;
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if (embd_phy) {
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if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
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return -1;
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} else {
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if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
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return -1;
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}
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rx_ctl = asix_read_rx_ctl(dev);
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debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
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if (asix_write_rx_ctl(dev, 0x0000) < 0)
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return -1;
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rx_ctl = asix_read_rx_ctl(dev);
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debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
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return 0;
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}
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/*
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* Asix callbacks
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*/
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static int asix_init(struct eth_device *eth, bd_t *bd)
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{
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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int timeout = 0;
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#define TIMEOUT_RESOLUTION 50 /* ms */
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int link_detected;
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debug("** %s()\n", __func__);
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dev->phy_id = asix_get_phy_addr(dev);
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if (dev->phy_id < 0)
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debug("Failed to read phy id\n");
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if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
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goto out_err;
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if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0)
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goto out_err;
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asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
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asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
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ADVERTISE_ALL | ADVERTISE_CSMA);
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mii_nway_restart(dev);
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if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
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goto out_err;
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if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
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AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
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AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
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debug("Write IPG,IPG1,IPG2 failed\n");
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goto out_err;
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}
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if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
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goto out_err;
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do {
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link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
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BMSR_LSTATUS;
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if (!link_detected) {
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if (timeout == 0)
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printf("Waiting for Ethernet connection... ");
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udelay(TIMEOUT_RESOLUTION * 1000);
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timeout += TIMEOUT_RESOLUTION;
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}
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} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
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if (link_detected) {
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if (timeout != 0)
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printf("done.\n");
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} else {
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printf("unable to connect.\n");
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goto out_err;
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}
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return 0;
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out_err:
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return -1;
|
|
}
|
|
|
|
static int asix_send(struct eth_device *eth, void *packet, int length)
|
|
{
|
|
struct ueth_data *dev = (struct ueth_data *)eth->priv;
|
|
int err;
|
|
u32 packet_len;
|
|
int actual_len;
|
|
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
|
|
PKTSIZE + sizeof(packet_len));
|
|
|
|
debug("** %s(), len %d\n", __func__, length);
|
|
|
|
packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
|
|
cpu_to_le32s(&packet_len);
|
|
|
|
memcpy(msg, &packet_len, sizeof(packet_len));
|
|
memcpy(msg + sizeof(packet_len), (void *)packet, length);
|
|
if (length & 1)
|
|
length++;
|
|
|
|
err = usb_bulk_msg(dev->pusb_dev,
|
|
usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
|
|
(void *)msg,
|
|
length + sizeof(packet_len),
|
|
&actual_len,
|
|
USB_BULK_SEND_TIMEOUT);
|
|
debug("Tx: len = %u, actual = %u, err = %d\n",
|
|
length + sizeof(packet_len), actual_len, err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int asix_recv(struct eth_device *eth)
|
|
{
|
|
struct ueth_data *dev = (struct ueth_data *)eth->priv;
|
|
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
|
|
unsigned char *buf_ptr;
|
|
int err;
|
|
int actual_len;
|
|
u32 packet_len;
|
|
|
|
debug("** %s()\n", __func__);
|
|
|
|
err = usb_bulk_msg(dev->pusb_dev,
|
|
usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
|
|
(void *)recv_buf,
|
|
AX_RX_URB_SIZE,
|
|
&actual_len,
|
|
USB_BULK_RECV_TIMEOUT);
|
|
debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
|
|
actual_len, err);
|
|
if (err != 0) {
|
|
debug("Rx: failed to receive\n");
|
|
return -1;
|
|
}
|
|
if (actual_len > AX_RX_URB_SIZE) {
|
|
debug("Rx: received too many bytes %d\n", actual_len);
|
|
return -1;
|
|
}
|
|
|
|
buf_ptr = recv_buf;
|
|
while (actual_len > 0) {
|
|
/*
|
|
* 1st 4 bytes contain the length of the actual data as two
|
|
* complementary 16-bit words. Extract the length of the data.
|
|
*/
|
|
if (actual_len < sizeof(packet_len)) {
|
|
debug("Rx: incomplete packet length\n");
|
|
return -1;
|
|
}
|
|
memcpy(&packet_len, buf_ptr, sizeof(packet_len));
|
|
le32_to_cpus(&packet_len);
|
|
if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
|
|
debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
|
|
packet_len, (~packet_len >> 16) & 0x7ff,
|
|
packet_len & 0x7ff);
|
|
return -1;
|
|
}
|
|
packet_len = packet_len & 0x7ff;
|
|
if (packet_len > actual_len - sizeof(packet_len)) {
|
|
debug("Rx: too large packet: %d\n", packet_len);
|
|
return -1;
|
|
}
|
|
|
|
/* Notify net stack */
|
|
NetReceive(buf_ptr + sizeof(packet_len), packet_len);
|
|
|
|
/* Adjust for next iteration. Packets are padded to 16-bits */
|
|
if (packet_len & 1)
|
|
packet_len++;
|
|
actual_len -= sizeof(packet_len) + packet_len;
|
|
buf_ptr += sizeof(packet_len) + packet_len;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void asix_halt(struct eth_device *eth)
|
|
{
|
|
debug("** %s()\n", __func__);
|
|
}
|
|
|
|
/*
|
|
* Asix probing functions
|
|
*/
|
|
void asix_eth_before_probe(void)
|
|
{
|
|
curr_eth_dev = 0;
|
|
}
|
|
|
|
struct asix_dongle {
|
|
unsigned short vendor;
|
|
unsigned short product;
|
|
int flags;
|
|
};
|
|
|
|
static const struct asix_dongle const asix_dongles[] = {
|
|
{ 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
|
|
{ 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
|
|
/* Cables-to-Go USB Ethernet Adapter */
|
|
{ 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
|
|
{ 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
|
|
{ 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
|
|
{ 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
|
|
{ 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
|
|
{ 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
|
|
/* DLink DUB-E100 H/W Ver B1 Alternate */
|
|
{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
|
|
/* ASIX 88772B */
|
|
{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
|
|
{ 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
|
|
};
|
|
|
|
/* Probe to see if a new device is actually an asix device */
|
|
int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
|
|
struct ueth_data *ss)
|
|
{
|
|
struct usb_interface *iface;
|
|
struct usb_interface_descriptor *iface_desc;
|
|
int ep_in_found = 0, ep_out_found = 0;
|
|
int i;
|
|
|
|
/* let's examine the device now */
|
|
iface = &dev->config.if_desc[ifnum];
|
|
iface_desc = &dev->config.if_desc[ifnum].desc;
|
|
|
|
for (i = 0; asix_dongles[i].vendor != 0; i++) {
|
|
if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
|
|
dev->descriptor.idProduct == asix_dongles[i].product)
|
|
/* Found a supported dongle */
|
|
break;
|
|
}
|
|
|
|
if (asix_dongles[i].vendor == 0)
|
|
return 0;
|
|
|
|
memset(ss, 0, sizeof(struct ueth_data));
|
|
|
|
/* At this point, we know we've got a live one */
|
|
debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
|
|
dev->descriptor.idVendor, dev->descriptor.idProduct);
|
|
|
|
/* Initialize the ueth_data structure with some useful info */
|
|
ss->ifnum = ifnum;
|
|
ss->pusb_dev = dev;
|
|
ss->subclass = iface_desc->bInterfaceSubClass;
|
|
ss->protocol = iface_desc->bInterfaceProtocol;
|
|
|
|
/* alloc driver private */
|
|
ss->dev_priv = calloc(1, sizeof(struct asix_private));
|
|
if (!ss->dev_priv)
|
|
return 0;
|
|
|
|
((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
|
|
|
|
/*
|
|
* We are expecting a minimum of 3 endpoints - in, out (bulk), and
|
|
* int. We will ignore any others.
|
|
*/
|
|
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
|
|
/* is it an BULK endpoint? */
|
|
if ((iface->ep_desc[i].bmAttributes &
|
|
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
|
|
u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
|
|
if (ep_addr & USB_DIR_IN) {
|
|
if (!ep_in_found) {
|
|
ss->ep_in = ep_addr &
|
|
USB_ENDPOINT_NUMBER_MASK;
|
|
ep_in_found = 1;
|
|
}
|
|
} else {
|
|
if (!ep_out_found) {
|
|
ss->ep_out = ep_addr &
|
|
USB_ENDPOINT_NUMBER_MASK;
|
|
ep_out_found = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* is it an interrupt endpoint? */
|
|
if ((iface->ep_desc[i].bmAttributes &
|
|
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
|
|
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
|
|
USB_ENDPOINT_NUMBER_MASK;
|
|
ss->irqinterval = iface->ep_desc[i].bInterval;
|
|
}
|
|
}
|
|
debug("Endpoints In %d Out %d Int %d\n",
|
|
ss->ep_in, ss->ep_out, ss->ep_int);
|
|
|
|
/* Do some basic sanity checks, and bail if we find a problem */
|
|
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
|
|
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
|
|
debug("Problems with device\n");
|
|
return 0;
|
|
}
|
|
dev->privptr = (void *)ss;
|
|
return 1;
|
|
}
|
|
|
|
int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
|
|
struct eth_device *eth)
|
|
{
|
|
struct asix_private *priv = (struct asix_private *)ss->dev_priv;
|
|
|
|
if (!eth) {
|
|
debug("%s: missing parameter.\n", __func__);
|
|
return 0;
|
|
}
|
|
sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
|
|
eth->init = asix_init;
|
|
eth->send = asix_send;
|
|
eth->recv = asix_recv;
|
|
eth->halt = asix_halt;
|
|
if (!(priv->flags & FLAG_TYPE_AX88172))
|
|
eth->write_hwaddr = asix_write_hwaddr;
|
|
eth->priv = ss;
|
|
|
|
if (asix_basic_reset(ss))
|
|
return 0;
|
|
|
|
/* Get the MAC address */
|
|
if (asix_read_mac(eth))
|
|
return 0;
|
|
debug("MAC %pM\n", eth->enetaddr);
|
|
|
|
return 1;
|
|
}
|