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c3754e9cc2
This patch adds support for BCH8 error correction code to omap_gpmc driver. We use GPMC to generate codes/syndromes but we need ELM to find error locations from given syndrome. Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com> [ilya: merge it with omap_gpmc driver, some fixes and cleanup] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
777 lines
21 KiB
C
777 lines
21 KiB
C
/*
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* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
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* Rohit Choraria <rohitkc@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/omap_gpmc.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/compiler.h>
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#include <nand.h>
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#ifdef CONFIG_AM33XX
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#include <asm/arch/elm.h>
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#endif
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static uint8_t cs;
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static __maybe_unused struct nand_ecclayout hw_nand_oob =
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GPMC_NAND_HW_ECC_LAYOUT;
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/*
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* omap_nand_hwcontrol - Set the address pointers corretly for the
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* following address/data/command operation
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*/
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static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
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uint32_t ctrl)
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{
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register struct nand_chip *this = mtd->priv;
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/*
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* Point the IO_ADDR to DATA and ADDRESS registers instead
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* of chip address
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*/
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switch (ctrl) {
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case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
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this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
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break;
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case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
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this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
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break;
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case NAND_CTRL_CHANGE | NAND_NCE:
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this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
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break;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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#ifdef CONFIG_SPL_BUILD
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/* Check wait pin as dev ready indicator */
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int omap_spl_dev_ready(struct mtd_info *mtd)
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{
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return gpmc_cfg->status & (1 << 8);
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}
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#endif
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/*
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* omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
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* GPMC controller
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* @mtd: MTD device structure
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*
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*/
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static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
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{
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/*
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* Init ECC Control Register
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* Clear all ECC | Enable Reg1
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*/
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
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}
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/*
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* gen_true_ecc - This function will generate true ECC value, which
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* can be used when correcting data read from NAND flash memory core
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*
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* @ecc_buf: buffer to store ecc code
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*
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* @return: re-formatted ECC value
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*/
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static uint32_t gen_true_ecc(uint8_t *ecc_buf)
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{
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return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
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((ecc_buf[2] & 0x0F) << 8);
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}
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/*
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* omap_correct_data - Compares the ecc read from nand spare area with ECC
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* registers values and corrects one bit error if it has occured
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* Further details can be had from OMAP TRM and the following selected links:
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* http://en.wikipedia.org/wiki/Hamming_code
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* http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
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*
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* @mtd: MTD device structure
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* @dat: page data
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* @read_ecc: ecc read from nand flash
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* @calc_ecc: ecc read from ECC registers
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*
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* @return 0 if data is OK or corrected, else returns -1
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*/
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static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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uint32_t orig_ecc, new_ecc, res, hm;
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uint16_t parity_bits, byte;
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uint8_t bit;
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/* Regenerate the orginal ECC */
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orig_ecc = gen_true_ecc(read_ecc);
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new_ecc = gen_true_ecc(calc_ecc);
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/* Get the XOR of real ecc */
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res = orig_ecc ^ new_ecc;
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if (res) {
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/* Get the hamming width */
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hm = hweight32(res);
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/* Single bit errors can be corrected! */
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if (hm == 12) {
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/* Correctable data! */
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parity_bits = res >> 16;
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bit = (parity_bits & 0x7);
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byte = (parity_bits >> 3) & 0x1FF;
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/* Flip the bit to correct */
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dat[byte] ^= (0x1 << bit);
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} else if (hm == 1) {
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printf("Error: Ecc is wrong\n");
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/* ECC itself is corrupted */
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return 2;
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} else {
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/*
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* hm distance != parity pairs OR one, could mean 2 bit
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* error OR potentially be on a blank page..
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* orig_ecc: contains spare area data from nand flash.
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* new_ecc: generated ecc while reading data area.
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* Note: if the ecc = 0, all data bits from which it was
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* generated are 0xFF.
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* The 3 byte(24 bits) ecc is generated per 512byte
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* chunk of a page. If orig_ecc(from spare area)
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* is 0xFF && new_ecc(computed now from data area)=0x0,
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* this means that data area is 0xFF and spare area is
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* 0xFF. A sure sign of a erased page!
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*/
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if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
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return 0;
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printf("Error: Bad compare! failed\n");
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/* detected 2 bit error */
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return -1;
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}
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}
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return 0;
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}
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/*
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* omap_calculate_ecc - Generate non-inverted ECC bytes.
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*
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* Using noninverted ECC can be considered ugly since writing a blank
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* page ie. padding will clear the ECC bytes. This is no problem as
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* long nobody is trying to write data on the seemingly unused page.
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* Reading an erased page will produce an ECC mismatch between
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* generated and read ECC bytes that has to be dealt with separately.
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* E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
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* is used, the result of read will be 0x0 while the ECC offsets of the
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* spare area will be 0xFF which will result in an ECC mismatch.
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
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const uint8_t *dat, uint8_t *ecc_code)
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{
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u_int32_t val;
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/* Start Reading from HW ECC1_Result = 0x200 */
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val = readl(&gpmc_cfg->ecc1_result);
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ecc_code[0] = val & 0xFF;
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ecc_code[1] = (val >> 16) & 0xFF;
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ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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writel(0x000, &gpmc_cfg->ecc_config);
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return 0;
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}
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/*
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* omap_enable_ecc - This function enables the hardware ecc functionality
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
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{
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struct nand_chip *chip = mtd->priv;
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uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
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switch (mode) {
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case NAND_ECC_READ:
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case NAND_ECC_WRITE:
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/* Clear the ecc result registers, select ecc reg as 1 */
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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/*
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* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
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* tell all regs to generate size0 sized regs
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* we just have a single ECC engine for all CS
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*/
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writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
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&gpmc_cfg->ecc_size_config);
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val = (dev_width << 7) | (cs << 1) | (0x1);
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writel(val, &gpmc_cfg->ecc_config);
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break;
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default:
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printf("Error: Unrecognized Mode[%d]!\n", mode);
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break;
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}
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}
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/*
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* BCH8 support (needs ELM and thus AM33xx-only)
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*/
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#ifdef CONFIG_AM33XX
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struct nand_bch_priv {
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uint8_t mode;
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uint8_t type;
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uint8_t nibbles;
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};
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/* bch types */
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#define ECC_BCH4 0
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#define ECC_BCH8 1
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#define ECC_BCH16 2
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/* BCH nibbles for diff bch levels */
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#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
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#define ECC_BCH4_NIBBLES 13
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#define ECC_BCH8_NIBBLES 26
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#define ECC_BCH16_NIBBLES 52
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static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
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static struct nand_bch_priv bch_priv = {
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.mode = NAND_ECC_HW_BCH,
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.type = ECC_BCH8,
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.nibbles = ECC_BCH8_NIBBLES
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};
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/*
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* omap_read_bch8_result - Read BCH result for BCH8 level
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*
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* @mtd: MTD device structure
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* @big_endian: When set read register 3 first
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* @ecc_code: Read syndrome from BCH result registers
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*/
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static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
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uint8_t *ecc_code)
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{
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uint32_t *ptr;
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int8_t i = 0, j;
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if (big_endian) {
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ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
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ecc_code[i++] = readl(ptr) & 0xFF;
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ptr--;
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for (j = 0; j < 3; j++) {
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ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
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ecc_code[i++] = readl(ptr) & 0xFF;
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ptr--;
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}
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} else {
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ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
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for (j = 0; j < 3; j++) {
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ecc_code[i++] = readl(ptr) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
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ptr++;
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}
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ecc_code[i++] = readl(ptr) & 0xFF;
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ecc_code[i++] = 0; /* 14th byte is always zero */
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}
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}
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/*
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* omap_ecc_disable - Disable H/W ECC calculation
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*
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* @mtd: MTD device structure
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*
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*/
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static void omap_ecc_disable(struct mtd_info *mtd)
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{
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writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
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&gpmc_cfg->ecc_config);
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}
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/*
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* omap_rotate_ecc_bch - Rotate the syndrome bytes
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*
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* @mtd: MTD device structure
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* @calc_ecc: ECC read from ECC registers
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* @syndrome: Rotated syndrome will be retuned in this array
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*
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*/
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static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
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uint8_t *syndrome)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t n_bytes = 0;
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int8_t i, j;
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switch (bch->type) {
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case ECC_BCH4:
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n_bytes = 8;
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break;
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case ECC_BCH16:
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n_bytes = 28;
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break;
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case ECC_BCH8:
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default:
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n_bytes = 13;
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break;
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}
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for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
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syndrome[i] = calc_ecc[j];
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}
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/*
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* omap_calculate_ecc_bch - Read BCH ECC result
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*
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t big_endian = 1;
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int8_t ret = 0;
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if (bch->type == ECC_BCH8)
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omap_read_bch8_result(mtd, big_endian, ecc_code);
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else /* BCH4 and BCH16 currently not supported */
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ret = -1;
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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omap_ecc_disable(mtd);
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return ret;
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}
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/*
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* omap_fix_errors_bch - Correct bch error in the data
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*
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* @mtd: MTD device structure
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* @data: Data read from flash
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* @error_count:Number of errors in data
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* @error_loc: Locations of errors in the data
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*
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*/
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static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
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uint32_t error_count, uint32_t *error_loc)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t count = 0;
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uint32_t error_byte_pos;
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uint32_t error_bit_mask;
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uint32_t last_bit = (bch->nibbles * 4) - 1;
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/* Flip all bits as specified by the error location array. */
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/* FOR( each found error location flip the bit ) */
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for (count = 0; count < error_count; count++) {
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if (error_loc[count] > last_bit) {
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/* Remove the ECC spare bits from correction. */
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error_loc[count] -= (last_bit + 1);
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/* Offset bit in data region */
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error_byte_pos = ((512 * 8) -
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(error_loc[count]) - 1) / 8;
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/* Error Bit mask */
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error_bit_mask = 0x1 << (error_loc[count] % 8);
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/* Toggle the error bit to make the correction. */
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data[error_byte_pos] ^= error_bit_mask;
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}
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}
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}
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/*
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* omap_correct_data_bch - Compares the ecc read from nand spare area
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* with ECC registers values and corrects one bit error if it has occured
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*
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* @mtd: MTD device structure
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* @dat: page data
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* @read_ecc: ecc read from nand flash (ignored)
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* @calc_ecc: ecc read from ECC registers
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*
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* @return 0 if data is OK or corrected, else returns -1
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*/
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static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t syndrome[28];
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uint32_t error_count = 0;
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uint32_t error_loc[8];
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uint32_t i, ecc_flag;
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ecc_flag = 0;
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for (i = 0; i < chip->ecc.bytes; i++)
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if (read_ecc[i] != 0xff)
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ecc_flag = 1;
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if (!ecc_flag)
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return 0;
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elm_reset();
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elm_config((enum bch_level)(bch->type));
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/*
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* while reading ECC result we read it in big endian.
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* Hence while loading to ELM we have rotate to get the right endian.
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*/
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omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
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/* use elm module to check for errors */
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if (elm_check_error(syndrome, bch->nibbles, &error_count,
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error_loc) != 0) {
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printf("ECC: uncorrectable.\n");
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return -1;
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}
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/* correct bch error */
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if (error_count > 0)
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omap_fix_errors_bch(mtd, dat, error_count, error_loc);
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return 0;
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}
|
|
/*
|
|
* omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
|
|
* GPMC controller
|
|
* @mtd: MTD device structure
|
|
* @mode: Read/Write mode
|
|
*/
|
|
static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
|
|
{
|
|
uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
|
|
uint32_t unused_length = 0;
|
|
struct nand_bch_priv *bch = chip->priv;
|
|
|
|
switch (bch->nibbles) {
|
|
case ECC_BCH4_NIBBLES:
|
|
unused_length = 3;
|
|
break;
|
|
case ECC_BCH8_NIBBLES:
|
|
unused_length = 2;
|
|
break;
|
|
case ECC_BCH16_NIBBLES:
|
|
unused_length = 0;
|
|
break;
|
|
}
|
|
|
|
/* Clear the ecc result registers, select ecc reg as 1 */
|
|
writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
|
|
|
|
switch (mode) {
|
|
case NAND_ECC_WRITE:
|
|
/* eccsize1 config */
|
|
val = ((unused_length + bch->nibbles) << 22);
|
|
break;
|
|
|
|
case NAND_ECC_READ:
|
|
default:
|
|
/* by default eccsize0 selected for ecc1resultsize */
|
|
/* eccsize0 config */
|
|
val = (bch->nibbles << 12);
|
|
/* eccsize1 config */
|
|
val |= (unused_length << 22);
|
|
break;
|
|
}
|
|
/* ecc size configuration */
|
|
writel(val, &gpmc_cfg->ecc_size_config);
|
|
/* by default 512bytes sector page is selected */
|
|
/* set bch mode */
|
|
val = (1 << 16);
|
|
/* bch4 / bch8 / bch16 */
|
|
val |= (bch->type << 12);
|
|
/* set wrap mode to 1 */
|
|
val |= (1 << 8);
|
|
val |= (dev_width << 7);
|
|
val |= (cs << 1);
|
|
writel(val, &gpmc_cfg->ecc_config);
|
|
}
|
|
|
|
/*
|
|
* omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
|
|
* @mtd: MTD device structure
|
|
* @mode: Read/Write mode
|
|
*
|
|
*/
|
|
static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
omap_hwecc_init_bch(chip, mode);
|
|
/* enable ecc */
|
|
writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
|
|
}
|
|
|
|
/**
|
|
* omap_read_page_bch - hardware ecc based page read function
|
|
* @mtd: mtd info structure
|
|
* @chip: nand chip info structure
|
|
* @buf: buffer to store read data
|
|
* @page: page number to read
|
|
*
|
|
*/
|
|
static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint8_t *buf, int page)
|
|
{
|
|
int i, eccsize = chip->ecc.size;
|
|
int eccbytes = chip->ecc.bytes;
|
|
int eccsteps = chip->ecc.steps;
|
|
uint8_t *p = buf;
|
|
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
|
uint8_t *ecc_code = chip->buffers->ecccode;
|
|
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
|
uint8_t *oob = chip->oob_poi;
|
|
uint32_t data_pos;
|
|
uint32_t oob_pos;
|
|
|
|
data_pos = 0;
|
|
/* oob area start */
|
|
oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
|
|
oob += chip->ecc.layout->eccpos[0];
|
|
|
|
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
|
|
oob += eccbytes) {
|
|
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
|
/* read data */
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
|
|
chip->read_buf(mtd, p, eccsize);
|
|
|
|
/* read respective ecc from oob area */
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
|
|
chip->read_buf(mtd, oob, eccbytes);
|
|
/* read syndrome */
|
|
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
|
|
|
data_pos += eccsize;
|
|
oob_pos += eccbytes;
|
|
}
|
|
|
|
for (i = 0; i < chip->ecc.total; i++)
|
|
ecc_code[i] = chip->oob_poi[eccpos[i]];
|
|
|
|
eccsteps = chip->ecc.steps;
|
|
p = buf;
|
|
|
|
for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
|
int stat;
|
|
|
|
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
|
|
if (stat < 0)
|
|
mtd->ecc_stats.failed++;
|
|
else
|
|
mtd->ecc_stats.corrected += stat;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_AM33XX */
|
|
|
|
#ifndef CONFIG_SPL_BUILD
|
|
/*
|
|
* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
|
|
* The default is to come up on s/w ecc
|
|
*
|
|
* @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
|
|
*
|
|
*/
|
|
void omap_nand_switch_ecc(int32_t hardware)
|
|
{
|
|
struct nand_chip *nand;
|
|
struct mtd_info *mtd;
|
|
|
|
if (nand_curr_device < 0 ||
|
|
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
|
|
!nand_info[nand_curr_device].name) {
|
|
printf("Error: Can't switch ecc, no devices available\n");
|
|
return;
|
|
}
|
|
|
|
mtd = &nand_info[nand_curr_device];
|
|
nand = mtd->priv;
|
|
|
|
nand->options |= NAND_OWN_BUFFERS;
|
|
|
|
/* Reset ecc interface */
|
|
nand->ecc.read_page = NULL;
|
|
nand->ecc.write_page = NULL;
|
|
nand->ecc.read_oob = NULL;
|
|
nand->ecc.write_oob = NULL;
|
|
nand->ecc.hwctl = NULL;
|
|
nand->ecc.correct = NULL;
|
|
nand->ecc.calculate = NULL;
|
|
|
|
/* Setup the ecc configurations again */
|
|
if (hardware == 1) {
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.layout = &hw_nand_oob;
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 3;
|
|
nand->ecc.hwctl = omap_enable_hwecc;
|
|
nand->ecc.correct = omap_correct_data;
|
|
nand->ecc.calculate = omap_calculate_ecc;
|
|
omap_hwecc_init(nand);
|
|
printf("HW ECC selected\n");
|
|
#ifdef CONFIG_AM33XX
|
|
} else if (hardware == 2) {
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.layout = &hw_bch8_nand_oob;
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 14;
|
|
nand->ecc.read_page = omap_read_page_bch;
|
|
nand->ecc.hwctl = omap_enable_ecc_bch;
|
|
nand->ecc.correct = omap_correct_data_bch;
|
|
nand->ecc.calculate = omap_calculate_ecc_bch;
|
|
omap_hwecc_init_bch(nand, NAND_ECC_READ);
|
|
printf("HW BCH8 selected\n");
|
|
#endif
|
|
} else {
|
|
nand->ecc.mode = NAND_ECC_SOFT;
|
|
/* Use mtd default settings */
|
|
nand->ecc.layout = NULL;
|
|
nand->ecc.size = 0;
|
|
printf("SW ECC selected\n");
|
|
}
|
|
|
|
/* Update NAND handling after ECC mode switch */
|
|
nand_scan_tail(mtd);
|
|
|
|
nand->options &= ~NAND_OWN_BUFFERS;
|
|
}
|
|
#endif /* CONFIG_SPL_BUILD */
|
|
|
|
/*
|
|
* Board-specific NAND initialization. The following members of the
|
|
* argument are board-specific:
|
|
* - IO_ADDR_R: address to read the 8 I/O lines of the flash device
|
|
* - IO_ADDR_W: address to write the 8 I/O lines of the flash device
|
|
* - cmd_ctrl: hardwarespecific function for accesing control-lines
|
|
* - waitfunc: hardwarespecific function for accesing device ready/busy line
|
|
* - ecc.hwctl: function to enable (reset) hardware ecc generator
|
|
* - ecc.mode: mode of ecc, see defines
|
|
* - chip_delay: chip dependent delay for transfering data from array to
|
|
* read regs (tR)
|
|
* - options: various chip options. They can partly be set to inform
|
|
* nand_scan about special functionality. See the defines for further
|
|
* explanation
|
|
*/
|
|
int board_nand_init(struct nand_chip *nand)
|
|
{
|
|
int32_t gpmc_config = 0;
|
|
cs = 0;
|
|
|
|
/*
|
|
* xloader/Uboot's gpmc configuration would have configured GPMC for
|
|
* nand type of memory. The following logic scans and latches on to the
|
|
* first CS with NAND type memory.
|
|
* TBD: need to make this logic generic to handle multiple CS NAND
|
|
* devices.
|
|
*/
|
|
while (cs < GPMC_MAX_CS) {
|
|
/* Check if NAND type is set */
|
|
if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
|
|
/* Found it!! */
|
|
break;
|
|
}
|
|
cs++;
|
|
}
|
|
if (cs >= GPMC_MAX_CS) {
|
|
printf("NAND: Unable to find NAND settings in "
|
|
"GPMC Configuration - quitting\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
gpmc_config = readl(&gpmc_cfg->config);
|
|
/* Disable Write protect */
|
|
gpmc_config |= 0x10;
|
|
writel(gpmc_config, &gpmc_cfg->config);
|
|
|
|
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
|
|
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
|
|
|
|
nand->cmd_ctrl = omap_nand_hwcontrol;
|
|
nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
|
|
/* If we are 16 bit dev, our gpmc config tells us that */
|
|
if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
|
|
nand->options |= NAND_BUSWIDTH_16;
|
|
|
|
nand->chip_delay = 100;
|
|
|
|
#ifdef CONFIG_AM33XX
|
|
/* required in case of BCH */
|
|
elm_init();
|
|
|
|
/* BCH info that will be correct for SPL or overridden otherwise. */
|
|
nand->priv = &bch_priv;
|
|
#endif
|
|
|
|
/* Default ECC mode */
|
|
#ifdef CONFIG_AM33XX
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.layout = &hw_bch8_nand_oob;
|
|
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
|
|
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
|
|
nand->ecc.hwctl = omap_enable_ecc_bch;
|
|
nand->ecc.correct = omap_correct_data_bch;
|
|
nand->ecc.calculate = omap_calculate_ecc_bch;
|
|
nand->ecc.read_page = omap_read_page_bch;
|
|
omap_hwecc_init_bch(nand, NAND_ECC_READ);
|
|
#else
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
|
|
nand->ecc.mode = NAND_ECC_SOFT;
|
|
#else
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.layout = &hw_nand_oob;
|
|
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
|
|
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
|
|
nand->ecc.hwctl = omap_enable_hwecc;
|
|
nand->ecc.correct = omap_correct_data;
|
|
nand->ecc.calculate = omap_calculate_ecc;
|
|
omap_hwecc_init(nand);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
if (nand->options & NAND_BUSWIDTH_16)
|
|
nand->read_buf = nand_read_buf16;
|
|
else
|
|
nand->read_buf = nand_read_buf;
|
|
nand->dev_ready = omap_spl_dev_ready;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|