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0f64057b4f
Import cvmx-pko3.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
786 lines
23 KiB
C
786 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*/
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#include <errno.h>
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#include <log.h>
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#include <time.h>
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#include <linux/delay.h>
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#include <mach/cvmx-regs.h>
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#include <mach/cvmx-csr.h>
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#include <mach/cvmx-bootmem.h>
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#include <mach/octeon-model.h>
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#include <mach/cvmx-fuse.h>
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#include <mach/octeon-feature.h>
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#include <mach/cvmx-qlm.h>
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#include <mach/octeon_qlm.h>
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#include <mach/cvmx-pcie.h>
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#include <mach/cvmx-coremask.h>
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#include <mach/cvmx-agl-defs.h>
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#include <mach/cvmx-bgxx-defs.h>
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#include <mach/cvmx-ciu-defs.h>
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#include <mach/cvmx-gmxx-defs.h>
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#include <mach/cvmx-gserx-defs.h>
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#include <mach/cvmx-ilk-defs.h>
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#include <mach/cvmx-ipd-defs.h>
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#include <mach/cvmx-pcsx-defs.h>
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#include <mach/cvmx-pcsxx-defs.h>
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#include <mach/cvmx-pki-defs.h>
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#include <mach/cvmx-pko-defs.h>
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#include <mach/cvmx-xcv-defs.h>
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#include <mach/cvmx-hwpko.h>
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#include <mach/cvmx-ilk.h>
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#include <mach/cvmx-pki.h>
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#include <mach/cvmx-pko3.h>
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#include <mach/cvmx-pko3-queue.h>
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#include <mach/cvmx-pko3-resources.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-board.h>
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#include <mach/cvmx-helper-cfg.h>
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#include <mach/cvmx-helper-bgx.h>
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#include <mach/cvmx-helper-cfg.h>
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#include <mach/cvmx-helper-util.h>
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#include <mach/cvmx-helper-pki.h>
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static const int debug;
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#define CVMX_DUMP_REGX(reg) \
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if (debug) \
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debug("%s=%#llx\n", #reg, (long long)csr_rd_node(node, reg))
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static int cvmx_pko_setup_macs(int node);
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/*
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* PKO descriptor queue operation error string
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*
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* @param dqstatus is the enumeration returned from hardware,
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* PKO_QUERY_RTN_S[DQSTATUS].
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*
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* @return static constant string error description
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*/
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const char *pko_dqstatus_error(pko_query_dqstatus_t dqstatus)
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{
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char *str = "PKO Undefined error";
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switch (dqstatus) {
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case PKO_DQSTATUS_PASS:
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str = "No error";
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break;
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case PKO_DQSTATUS_BADSTATE:
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str = "PKO queue not ready";
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break;
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case PKO_DQSTATUS_NOFPABUF:
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str = "PKO failed to allocate buffer from FPA";
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break;
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case PKO_DQSTATUS_NOPKOBUF:
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str = "PKO out of buffers";
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break;
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case PKO_DQSTATUS_FAILRTNPTR:
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str = "PKO failed to return buffer to FPA";
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break;
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case PKO_DQSTATUS_ALREADY:
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str = "PKO queue already opened";
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break;
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case PKO_DQSTATUS_NOTCREATED:
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str = "PKO queue has not been created";
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break;
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case PKO_DQSTATUS_NOTEMPTY:
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str = "PKO queue is not empty";
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break;
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case PKO_DQSTATUS_SENDPKTDROP:
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str = "Illegal PKO command construct";
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break;
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}
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return str;
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}
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/*
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* PKO global initialization for 78XX.
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*
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* @param node is the node on which PKO block is initialized.
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* @return none.
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*/
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int cvmx_pko3_hw_init_global(int node, uint16_t aura)
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{
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cvmx_pko_dpfi_flush_t pko_flush;
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cvmx_pko_dpfi_fpa_aura_t pko_aura;
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cvmx_pko_dpfi_ena_t dpfi_enable;
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cvmx_pko_ptf_iobp_cfg_t ptf_iobp_cfg;
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cvmx_pko_pdm_cfg_t pko_pdm_cfg;
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cvmx_pko_enable_t pko_enable;
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cvmx_pko_dpfi_status_t dpfi_status;
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cvmx_pko_status_t pko_status;
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cvmx_pko_shaper_cfg_t shaper_cfg;
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u64 cycles;
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const unsigned int timeout = 100; /* 100 milliseconds */
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if (node != (aura >> 10))
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cvmx_printf("WARNING: AURA vs PKO node mismatch\n");
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pko_enable.u64 = csr_rd_node(node, CVMX_PKO_ENABLE);
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if (pko_enable.s.enable) {
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cvmx_printf("WARNING: %s: PKO already enabled on node %u\n",
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__func__, node);
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return 0;
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}
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/* Enable color awareness. */
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shaper_cfg.u64 = csr_rd_node(node, CVMX_PKO_SHAPER_CFG);
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shaper_cfg.s.color_aware = 1;
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csr_wr_node(node, CVMX_PKO_SHAPER_CFG, shaper_cfg.u64);
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/* Clear FLUSH command to be sure */
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pko_flush.u64 = 0;
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pko_flush.s.flush_en = 0;
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csr_wr_node(node, CVMX_PKO_DPFI_FLUSH, pko_flush.u64);
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/* set the aura number in pko, use aura node from parameter */
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pko_aura.u64 = 0;
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pko_aura.s.node = aura >> 10;
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pko_aura.s.laura = aura;
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csr_wr_node(node, CVMX_PKO_DPFI_FPA_AURA, pko_aura.u64);
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CVMX_DUMP_REGX(CVMX_PKO_DPFI_FPA_AURA);
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dpfi_enable.u64 = 0;
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dpfi_enable.s.enable = 1;
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csr_wr_node(node, CVMX_PKO_DPFI_ENA, dpfi_enable.u64);
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/* Prepare timeout */
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cycles = get_timer(0);
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/* Wait until all pointers have been returned */
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do {
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pko_status.u64 = csr_rd_node(node, CVMX_PKO_STATUS);
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if (get_timer(cycles) > timeout)
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break;
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} while (!pko_status.s.pko_rdy);
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if (!pko_status.s.pko_rdy) {
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dpfi_status.u64 = csr_rd_node(node, CVMX_PKO_DPFI_STATUS);
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cvmx_printf("ERROR: %s: PKO DFPI failed, PKO_STATUS=%#llx DPFI_STATUS=%#llx\n",
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__func__, (unsigned long long)pko_status.u64,
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(unsigned long long)dpfi_status.u64);
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return -1;
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}
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/* Set max outstanding requests in IOBP for any FIFO.*/
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ptf_iobp_cfg.u64 = csr_rd_node(node, CVMX_PKO_PTF_IOBP_CFG);
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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ptf_iobp_cfg.s.max_read_size = 0x10; /* Recommended by HRM.*/
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else
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/* Reduce the value from recommended 0x10 to avoid
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* getting "underflow" condition in the BGX TX FIFO.
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*/
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ptf_iobp_cfg.s.max_read_size = 3;
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csr_wr_node(node, CVMX_PKO_PTF_IOBP_CFG, ptf_iobp_cfg.u64);
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/* Set minimum packet size per Ethernet standard */
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pko_pdm_cfg.u64 = 0;
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pko_pdm_cfg.s.pko_pad_minlen = 0x3c; /* 60 bytes before FCS */
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csr_wr_node(node, CVMX_PKO_PDM_CFG, pko_pdm_cfg.u64);
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/* Initialize MACs and FIFOs */
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cvmx_pko_setup_macs(node);
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/* enable PKO, although interfaces and queues are not up yet */
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pko_enable.u64 = 0;
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pko_enable.s.enable = 1;
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csr_wr_node(node, CVMX_PKO_ENABLE, pko_enable.u64);
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/* PKO_RDY set indicates successful initialization */
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pko_status.u64 = csr_rd_node(node, CVMX_PKO_STATUS);
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if (pko_status.s.pko_rdy)
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return 0;
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cvmx_printf("ERROR: %s: failed, PKO_STATUS=%#llx\n", __func__,
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(unsigned long long)pko_status.u64);
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return -1;
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}
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/*
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* Configure Channel credit level in PKO.
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*
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* @param node is to specify the node to which this configuration is applied.
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* @param level specifies the level at which pko channel queues will be configured,
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* @return returns 0 if successful and -1 on failure.
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*/
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int cvmx_pko3_channel_credit_level(int node, enum cvmx_pko3_level_e level)
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{
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union cvmx_pko_channel_level channel_level;
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channel_level.u64 = 0;
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if (level == CVMX_PKO_L2_QUEUES)
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channel_level.s.cc_level = 0;
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else if (level == CVMX_PKO_L3_QUEUES)
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channel_level.s.cc_level = 1;
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else
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return -1;
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csr_wr_node(node, CVMX_PKO_CHANNEL_LEVEL, channel_level.u64);
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return 0;
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}
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/** Open configured descriptor queues before queueing packets into them.
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*
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* @param node is to specify the node to which this configuration is applied.
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* @param dq is the descriptor queue number to be opened.
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* @return returns 0 on success or -1 on failure.
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*/
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int cvmx_pko_dq_open(int node, int dq)
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{
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cvmx_pko_query_rtn_t pko_status;
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pko_query_dqstatus_t dqstatus;
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cvmx_pko3_dq_params_t *p_param;
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if (debug)
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debug("%s: DEBUG: dq %u\n", __func__, dq);
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__cvmx_pko3_dq_param_setup(node);
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pko_status = __cvmx_pko3_do_dma(node, dq, NULL, 0, CVMX_PKO_DQ_OPEN);
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dqstatus = pko_status.s.dqstatus;
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if (dqstatus == PKO_DQSTATUS_ALREADY)
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return 0;
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if (dqstatus != PKO_DQSTATUS_PASS) {
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cvmx_printf("%s: ERROR: Failed to open dq :%u: %s\n", __func__,
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dq, pko_dqstatus_error(dqstatus));
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return -1;
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}
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/* Setup the descriptor queue software parameters */
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p_param = cvmx_pko3_dq_parameters(node, dq);
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if (p_param) {
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p_param->depth = pko_status.s.depth;
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if (p_param->limit == 0)
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p_param->limit = 1024; /* last-resort default */
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}
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return 0;
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}
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/*
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* PKO initialization of MACs and FIFOs
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*
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* All MACs are configured and assigned a specific FIFO,
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* and each FIFO is configured with size for a best utilization
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* of available FIFO resources.
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*
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* @param node is to specify which node's pko block for this setup.
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* @return returns 0 if successful and -1 on failure.
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*
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* Note: This function contains model-specific code.
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*/
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static int cvmx_pko_setup_macs(int node)
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{
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unsigned int interface;
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unsigned int port, num_ports;
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unsigned int mac_num, fifo, pri, cnt;
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cvmx_helper_interface_mode_t mode;
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const unsigned int num_interfaces =
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cvmx_helper_get_number_of_interfaces();
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u8 fifo_group_cfg[8];
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u8 fifo_group_spd[8];
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unsigned int fifo_count = 0;
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unsigned int max_fifos = 0, fifo_groups = 0;
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struct {
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u8 fifo_cnt;
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u8 fifo_id;
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u8 pri;
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u8 spd;
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u8 mac_fifo_cnt;
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} cvmx_pko3_mac_table[32];
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if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
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max_fifos = 28; /* exclusive of NULL FIFO */
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fifo_groups = 8; /* inclusive of NULL PTGF */
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}
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if (OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
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max_fifos = 16;
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fifo_groups = 5;
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}
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/* Initialize FIFO allocation table */
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memset(&fifo_group_cfg, 0, sizeof(fifo_group_cfg));
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memset(&fifo_group_spd, 0, sizeof(fifo_group_spd));
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memset(cvmx_pko3_mac_table, 0, sizeof(cvmx_pko3_mac_table));
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/* Initialize all MACs as disabled */
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for (mac_num = 0; mac_num < __cvmx_pko3_num_macs(); mac_num++) {
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cvmx_pko3_mac_table[mac_num].pri = 0;
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cvmx_pko3_mac_table[mac_num].fifo_cnt = 0;
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cvmx_pko3_mac_table[mac_num].fifo_id = 0x1f;
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}
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for (interface = 0; interface < num_interfaces; interface++) {
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int xiface =
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cvmx_helper_node_interface_to_xiface(node, interface);
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/* Interface type for ALL interfaces */
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mode = cvmx_helper_interface_get_mode(xiface);
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num_ports = cvmx_helper_interface_enumerate(xiface);
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if (mode == CVMX_HELPER_INTERFACE_MODE_DISABLED)
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continue;
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/*
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* Non-BGX interfaces:
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* Each of these interfaces has a single MAC really.
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*/
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if (mode == CVMX_HELPER_INTERFACE_MODE_ILK ||
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mode == CVMX_HELPER_INTERFACE_MODE_NPI ||
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mode == CVMX_HELPER_INTERFACE_MODE_LOOP)
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num_ports = 1;
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for (port = 0; port < num_ports; port++) {
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int i;
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/* Get the per-port mode for BGX-interfaces */
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if (interface < CVMX_HELPER_MAX_GMX)
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mode = cvmx_helper_bgx_get_mode(xiface, port);
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/* In MIXED mode, LMACs can run different protocols */
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/* convert interface/port to mac number */
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i = __cvmx_pko3_get_mac_num(xiface, port);
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if (i < 0 || i >= (int)__cvmx_pko3_num_macs()) {
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cvmx_printf("%s: ERROR: interface %d:%u port %d has no MAC %d/%d\n",
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__func__, node, interface, port, i,
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__cvmx_pko3_num_macs());
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continue;
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}
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if (mode == CVMX_HELPER_INTERFACE_MODE_RXAUI) {
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unsigned int bgx_fifo_size =
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__cvmx_helper_bgx_fifo_size(xiface,
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port);
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cvmx_pko3_mac_table[i].mac_fifo_cnt =
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bgx_fifo_size /
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(CVMX_BGX_TX_FIFO_SIZE / 4);
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cvmx_pko3_mac_table[i].pri = 2;
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cvmx_pko3_mac_table[i].spd = 10;
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cvmx_pko3_mac_table[i].fifo_cnt = 2;
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} else if (mode == CVMX_HELPER_INTERFACE_MODE_XLAUI) {
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unsigned int bgx_fifo_size =
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__cvmx_helper_bgx_fifo_size(xiface,
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port);
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cvmx_pko3_mac_table[i].mac_fifo_cnt =
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bgx_fifo_size /
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(CVMX_BGX_TX_FIFO_SIZE / 4);
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cvmx_pko3_mac_table[i].pri = 4;
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cvmx_pko3_mac_table[i].spd = 40;
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cvmx_pko3_mac_table[i].fifo_cnt = 4;
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} else if (mode == CVMX_HELPER_INTERFACE_MODE_XAUI) {
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unsigned int bgx_fifo_size =
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__cvmx_helper_bgx_fifo_size(xiface,
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port);
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cvmx_pko3_mac_table[i].mac_fifo_cnt =
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bgx_fifo_size /
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(CVMX_BGX_TX_FIFO_SIZE / 4);
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cvmx_pko3_mac_table[i].pri = 3;
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cvmx_pko3_mac_table[i].fifo_cnt = 4;
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/* DXAUI at 20G, or XAU at 10G */
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cvmx_pko3_mac_table[i].spd = 20;
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} else if (mode == CVMX_HELPER_INTERFACE_MODE_XFI) {
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unsigned int bgx_fifo_size =
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__cvmx_helper_bgx_fifo_size(xiface,
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port);
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cvmx_pko3_mac_table[i].mac_fifo_cnt =
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bgx_fifo_size /
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(CVMX_BGX_TX_FIFO_SIZE / 4);
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cvmx_pko3_mac_table[i].pri = 3;
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cvmx_pko3_mac_table[i].fifo_cnt = 4;
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cvmx_pko3_mac_table[i].spd = 10;
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} else if (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) {
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cvmx_pko3_mac_table[i].fifo_cnt = 1;
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cvmx_pko3_mac_table[i].pri = 1;
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cvmx_pko3_mac_table[i].spd = 1;
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cvmx_pko3_mac_table[i].mac_fifo_cnt = 1;
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} else if (mode == CVMX_HELPER_INTERFACE_MODE_ILK ||
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mode == CVMX_HELPER_INTERFACE_MODE_SRIO) {
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cvmx_pko3_mac_table[i].fifo_cnt = 4;
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cvmx_pko3_mac_table[i].pri = 3;
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/* ILK/SRIO: speed depends on lane count */
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cvmx_pko3_mac_table[i].spd = 40;
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cvmx_pko3_mac_table[i].mac_fifo_cnt = 4;
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} else if (mode == CVMX_HELPER_INTERFACE_MODE_NPI) {
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cvmx_pko3_mac_table[i].fifo_cnt = 4;
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cvmx_pko3_mac_table[i].pri = 2;
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/* Actual speed depends on PCIe lanes/mode */
|
|
cvmx_pko3_mac_table[i].spd = 50;
|
|
/* SLI Tx FIFO size to be revisitted */
|
|
cvmx_pko3_mac_table[i].mac_fifo_cnt = 1;
|
|
} else {
|
|
/* Other BGX interface modes: SGMII/RGMII */
|
|
unsigned int bgx_fifo_size =
|
|
__cvmx_helper_bgx_fifo_size(xiface,
|
|
port);
|
|
|
|
cvmx_pko3_mac_table[i].mac_fifo_cnt =
|
|
bgx_fifo_size /
|
|
(CVMX_BGX_TX_FIFO_SIZE / 4);
|
|
cvmx_pko3_mac_table[i].fifo_cnt = 1;
|
|
cvmx_pko3_mac_table[i].pri = 1;
|
|
cvmx_pko3_mac_table[i].spd = 1;
|
|
}
|
|
|
|
if (debug)
|
|
debug("%s: intf %d:%u port %u %s mac %02u cnt %u macfifo %uk spd %u\n",
|
|
__func__, node, interface, port,
|
|
cvmx_helper_interface_mode_to_string(mode),
|
|
i, cvmx_pko3_mac_table[i].fifo_cnt,
|
|
cvmx_pko3_mac_table[i].mac_fifo_cnt * 8,
|
|
cvmx_pko3_mac_table[i].spd);
|
|
|
|
} /* for port */
|
|
} /* for interface */
|
|
|
|
/* Count the number of requested FIFOs */
|
|
for (fifo_count = mac_num = 0; mac_num < __cvmx_pko3_num_macs();
|
|
mac_num++)
|
|
fifo_count += cvmx_pko3_mac_table[mac_num].fifo_cnt;
|
|
|
|
if (debug)
|
|
debug("%s: initially requested FIFO count %u\n", __func__,
|
|
fifo_count);
|
|
|
|
/* Heuristically trim FIFO count to fit in available number */
|
|
pri = 1;
|
|
cnt = 4;
|
|
while (fifo_count > max_fifos) {
|
|
for (mac_num = 0; mac_num < __cvmx_pko3_num_macs(); mac_num++) {
|
|
if (cvmx_pko3_mac_table[mac_num].fifo_cnt == cnt &&
|
|
cvmx_pko3_mac_table[mac_num].pri <= pri) {
|
|
cvmx_pko3_mac_table[mac_num].fifo_cnt >>= 1;
|
|
fifo_count -=
|
|
cvmx_pko3_mac_table[mac_num].fifo_cnt;
|
|
}
|
|
if (fifo_count <= max_fifos)
|
|
break;
|
|
}
|
|
if (pri >= 4) {
|
|
pri = 1;
|
|
cnt >>= 1;
|
|
} else {
|
|
pri++;
|
|
}
|
|
if (cnt == 0)
|
|
break;
|
|
}
|
|
|
|
if (debug)
|
|
debug("%s: adjusted FIFO count %u\n", __func__, fifo_count);
|
|
|
|
/* Special case for NULL Virtual FIFO */
|
|
fifo_group_cfg[fifo_groups - 1] = 0;
|
|
/* there is no MAC connected to NULL FIFO */
|
|
|
|
/* Configure MAC units, and attach a FIFO to each */
|
|
for (fifo = 0, cnt = 4; cnt > 0; cnt >>= 1) {
|
|
unsigned int g;
|
|
|
|
for (mac_num = 0; mac_num < __cvmx_pko3_num_macs(); mac_num++) {
|
|
if (cvmx_pko3_mac_table[mac_num].fifo_cnt < cnt ||
|
|
cvmx_pko3_mac_table[mac_num].fifo_id != 0x1f)
|
|
continue;
|
|
|
|
/* Attach FIFO to MAC */
|
|
cvmx_pko3_mac_table[mac_num].fifo_id = fifo;
|
|
g = fifo >> 2;
|
|
/* Sum speed for FIFO group */
|
|
fifo_group_spd[g] += cvmx_pko3_mac_table[mac_num].spd;
|
|
|
|
if (cnt == 4)
|
|
fifo_group_cfg[g] = 4; /* 10k,0,0,0 */
|
|
else if (cnt == 2 && (fifo & 0x3) == 0)
|
|
fifo_group_cfg[g] = 3; /* 5k,0,5k,0 */
|
|
else if (cnt == 2 && fifo_group_cfg[g] == 3)
|
|
/* no change */;
|
|
else if (cnt == 1 && (fifo & 0x2) &&
|
|
fifo_group_cfg[g] == 3)
|
|
fifo_group_cfg[g] = 1; /* 5k,0,2.5k 2.5k*/
|
|
else if (cnt == 1 && (fifo & 0x3) == 0x3)
|
|
/* no change */;
|
|
else if (cnt == 1)
|
|
fifo_group_cfg[g] = 0; /* 2.5k x 4 */
|
|
else
|
|
cvmx_printf("ERROR: %s: internal error\n",
|
|
__func__);
|
|
|
|
fifo += cnt;
|
|
}
|
|
}
|
|
|
|
/* Check if there was no error in FIFO allocation */
|
|
if (fifo > max_fifos) {
|
|
cvmx_printf("ERROR: %s: Internal error FIFO %u\n", __func__,
|
|
fifo);
|
|
return -1;
|
|
}
|
|
|
|
if (debug)
|
|
debug("%s: used %u of FIFOs\n", __func__, fifo);
|
|
|
|
/* Now configure all FIFO groups */
|
|
for (fifo = 0; fifo < fifo_groups; fifo++) {
|
|
cvmx_pko_ptgfx_cfg_t pko_ptgfx_cfg;
|
|
|
|
pko_ptgfx_cfg.u64 = csr_rd_node(node, CVMX_PKO_PTGFX_CFG(fifo));
|
|
if (pko_ptgfx_cfg.s.size != fifo_group_cfg[fifo])
|
|
pko_ptgfx_cfg.s.reset = 1;
|
|
pko_ptgfx_cfg.s.size = fifo_group_cfg[fifo];
|
|
if (fifo_group_spd[fifo] >= 40)
|
|
if (pko_ptgfx_cfg.s.size >= 3)
|
|
pko_ptgfx_cfg.s.rate = 3; /* 50 Gbps */
|
|
else
|
|
pko_ptgfx_cfg.s.rate = 2; /* 25 Gbps */
|
|
else if (fifo_group_spd[fifo] >= 20)
|
|
pko_ptgfx_cfg.s.rate = 2; /* 25 Gbps */
|
|
else if (fifo_group_spd[fifo] >= 10)
|
|
pko_ptgfx_cfg.s.rate = 1; /* 12.5 Gbps */
|
|
else
|
|
pko_ptgfx_cfg.s.rate = 0; /* 6.25 Gbps */
|
|
|
|
if (debug)
|
|
debug("%s: FIFO %#x-%#x size=%u speed=%d rate=%d\n",
|
|
__func__, fifo * 4, fifo * 4 + 3,
|
|
pko_ptgfx_cfg.s.size, fifo_group_spd[fifo],
|
|
pko_ptgfx_cfg.s.rate);
|
|
|
|
csr_wr_node(node, CVMX_PKO_PTGFX_CFG(fifo), pko_ptgfx_cfg.u64);
|
|
pko_ptgfx_cfg.s.reset = 0;
|
|
csr_wr_node(node, CVMX_PKO_PTGFX_CFG(fifo), pko_ptgfx_cfg.u64);
|
|
}
|
|
|
|
/* Configure all MACs assigned FIFO number */
|
|
for (mac_num = 0; mac_num < __cvmx_pko3_num_macs(); mac_num++) {
|
|
cvmx_pko_macx_cfg_t pko_mac_cfg;
|
|
|
|
if (debug)
|
|
debug("%s: mac#%02u: fifo=%#x cnt=%u speed=%d\n",
|
|
__func__, mac_num,
|
|
cvmx_pko3_mac_table[mac_num].fifo_id,
|
|
cvmx_pko3_mac_table[mac_num].fifo_cnt,
|
|
cvmx_pko3_mac_table[mac_num].spd);
|
|
|
|
pko_mac_cfg.u64 = csr_rd_node(node, CVMX_PKO_MACX_CFG(mac_num));
|
|
pko_mac_cfg.s.fifo_num = cvmx_pko3_mac_table[mac_num].fifo_id;
|
|
csr_wr_node(node, CVMX_PKO_MACX_CFG(mac_num), pko_mac_cfg.u64);
|
|
}
|
|
|
|
/* Setup PKO MCI0/MCI1/SKID credits */
|
|
for (mac_num = 0; mac_num < __cvmx_pko3_num_macs(); mac_num++) {
|
|
cvmx_pko_mci0_max_credx_t pko_mci0_max_cred;
|
|
cvmx_pko_mci1_max_credx_t pko_mci1_max_cred;
|
|
cvmx_pko_macx_cfg_t pko_mac_cfg;
|
|
unsigned int fifo_credit, mac_credit, skid_credit;
|
|
unsigned int pko_fifo_cnt, fifo_size;
|
|
unsigned int mac_fifo_cnt;
|
|
unsigned int tmp;
|
|
int saved_fifo_num;
|
|
|
|
pko_fifo_cnt = cvmx_pko3_mac_table[mac_num].fifo_cnt;
|
|
mac_fifo_cnt = cvmx_pko3_mac_table[mac_num].mac_fifo_cnt;
|
|
|
|
/* Skip unused MACs */
|
|
if (pko_fifo_cnt == 0)
|
|
continue;
|
|
|
|
/* Check for sanity */
|
|
if (pko_fifo_cnt > 4)
|
|
pko_fifo_cnt = 1;
|
|
|
|
fifo_size = (2 * 1024) + (1024 / 2); /* 2.5KiB */
|
|
fifo_credit = pko_fifo_cnt * fifo_size;
|
|
|
|
if (mac_num == 0) {
|
|
/* loopback */
|
|
mac_credit = 4096; /* From HRM Sec 13.0 */
|
|
skid_credit = 0;
|
|
} else if (mac_num == 1) {
|
|
/* DPI */
|
|
mac_credit = 2 * 1024;
|
|
skid_credit = 0;
|
|
} else if (octeon_has_feature(OCTEON_FEATURE_ILK) &&
|
|
(mac_num & 0xfe) == 2) {
|
|
/* ILK0, ILK1: MAC 2,3 */
|
|
mac_credit = 4 * 1024; /* 4KB fifo */
|
|
skid_credit = 0;
|
|
} else if (octeon_has_feature(OCTEON_FEATURE_SRIO) &&
|
|
(mac_num >= 6) && (mac_num <= 9)) {
|
|
/* SRIO0, SRIO1: MAC 6..9 */
|
|
mac_credit = 1024 / 2;
|
|
skid_credit = 0;
|
|
} else {
|
|
/* BGX */
|
|
mac_credit = mac_fifo_cnt * 8 * 1024;
|
|
skid_credit = mac_fifo_cnt * 256;
|
|
}
|
|
|
|
if (debug)
|
|
debug("%s: mac %u pko_fifo_credit=%u mac_credit=%u\n",
|
|
__func__, mac_num, fifo_credit, mac_credit);
|
|
|
|
tmp = (fifo_credit + mac_credit) / 16;
|
|
pko_mci0_max_cred.u64 = 0;
|
|
pko_mci0_max_cred.s.max_cred_lim = tmp;
|
|
|
|
/* Check for overflow */
|
|
if (pko_mci0_max_cred.s.max_cred_lim != tmp) {
|
|
cvmx_printf("WARNING: %s: MCI0 credit overflow\n",
|
|
__func__);
|
|
pko_mci0_max_cred.s.max_cred_lim = 0xfff;
|
|
}
|
|
|
|
/* Pass 2 PKO hardware does not use the MCI0 credits */
|
|
if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
|
|
csr_wr_node(node, CVMX_PKO_MCI0_MAX_CREDX(mac_num),
|
|
pko_mci0_max_cred.u64);
|
|
|
|
/* The original CSR formula is the correct one after all */
|
|
tmp = (mac_credit) / 16;
|
|
pko_mci1_max_cred.u64 = 0;
|
|
pko_mci1_max_cred.s.max_cred_lim = tmp;
|
|
|
|
/* Check for overflow */
|
|
if (pko_mci1_max_cred.s.max_cred_lim != tmp) {
|
|
cvmx_printf("WARNING: %s: MCI1 credit overflow\n",
|
|
__func__);
|
|
pko_mci1_max_cred.s.max_cred_lim = 0xfff;
|
|
}
|
|
|
|
csr_wr_node(node, CVMX_PKO_MCI1_MAX_CREDX(mac_num),
|
|
pko_mci1_max_cred.u64);
|
|
|
|
tmp = (skid_credit / 256) >> 1; /* valid 0,1,2 */
|
|
pko_mac_cfg.u64 = csr_rd_node(node, CVMX_PKO_MACX_CFG(mac_num));
|
|
|
|
/* The PKO_MACX_CFG bits cannot be changed unless FIFO_MUM=0x1f (unused fifo) */
|
|
saved_fifo_num = pko_mac_cfg.s.fifo_num;
|
|
pko_mac_cfg.s.fifo_num = 0x1f;
|
|
pko_mac_cfg.s.skid_max_cnt = tmp;
|
|
csr_wr_node(node, CVMX_PKO_MACX_CFG(mac_num), pko_mac_cfg.u64);
|
|
|
|
pko_mac_cfg.u64 = csr_rd_node(node, CVMX_PKO_MACX_CFG(mac_num));
|
|
pko_mac_cfg.s.fifo_num = saved_fifo_num;
|
|
csr_wr_node(node, CVMX_PKO_MACX_CFG(mac_num), pko_mac_cfg.u64);
|
|
|
|
if (debug) {
|
|
pko_mci0_max_cred.u64 =
|
|
csr_rd_node(node, CVMX_PKO_MCI0_MAX_CREDX(mac_num));
|
|
pko_mci1_max_cred.u64 =
|
|
csr_rd_node(node, CVMX_PKO_MCI1_MAX_CREDX(mac_num));
|
|
pko_mac_cfg.u64 =
|
|
csr_rd_node(node, CVMX_PKO_MACX_CFG(mac_num));
|
|
debug("%s: mac %u PKO_MCI0_MAX_CREDX=%u PKO_MCI1_MAX_CREDX=%u PKO_MACX_CFG[SKID_MAX_CNT]=%u\n",
|
|
__func__, mac_num,
|
|
pko_mci0_max_cred.s.max_cred_lim,
|
|
pko_mci1_max_cred.s.max_cred_lim,
|
|
pko_mac_cfg.s.skid_max_cnt);
|
|
}
|
|
} /* for mac_num */
|
|
|
|
return 0;
|
|
}
|
|
|
|
/** Set MAC options
|
|
*
|
|
* The options supported are the parameters below:
|
|
*
|
|
* @param xiface The physical interface number
|
|
* @param index The physical sub-interface port
|
|
* @param fcs_enable Enable FCS generation
|
|
* @param pad_enable Enable padding to minimum packet size
|
|
* @param fcs_sop_off Number of bytes at start of packet to exclude from FCS
|
|
*
|
|
* The typical use for `fcs_sop_off` is when the interface is configured
|
|
* to use a header such as HighGig to precede every Ethernet packet,
|
|
* such a header usually does not partake in the CRC32 computation stream,
|
|
* and its size must be set with this parameter.
|
|
*
|
|
* @return Returns 0 on success, -1 if interface/port is invalid.
|
|
*/
|
|
int cvmx_pko3_interface_options(int xiface, int index, bool fcs_enable,
|
|
bool pad_enable, unsigned int fcs_sop_off)
|
|
{
|
|
int mac_num;
|
|
cvmx_pko_macx_cfg_t pko_mac_cfg;
|
|
unsigned int fifo_num;
|
|
struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
|
|
|
|
if (debug)
|
|
debug("%s: intf %u:%u/%u fcs=%d pad=%d\n", __func__, xi.node,
|
|
xi.interface, index, fcs_enable, pad_enable);
|
|
|
|
mac_num = __cvmx_pko3_get_mac_num(xiface, index);
|
|
if (mac_num < 0) {
|
|
cvmx_printf("ERROR: %s: invalid interface %u:%u/%u\n", __func__,
|
|
xi.node, xi.interface, index);
|
|
return -1;
|
|
}
|
|
|
|
pko_mac_cfg.u64 = csr_rd_node(xi.node, CVMX_PKO_MACX_CFG(mac_num));
|
|
|
|
/* If MAC is not assigned, return an error */
|
|
if (pko_mac_cfg.s.fifo_num == 0x1f) {
|
|
cvmx_printf("ERROR: %s: unused interface %u:%u/%u\n", __func__,
|
|
xi.node, xi.interface, index);
|
|
return -1;
|
|
}
|
|
|
|
if (pko_mac_cfg.s.min_pad_ena == pad_enable &&
|
|
pko_mac_cfg.s.fcs_ena == fcs_enable) {
|
|
if (debug)
|
|
debug("%s: mac %#x unchanged\n", __func__, mac_num);
|
|
return 0;
|
|
}
|
|
|
|
/* WORKAROUND: Pass1 won't allow change any bits unless FIFO_NUM=0x1f */
|
|
fifo_num = pko_mac_cfg.s.fifo_num;
|
|
pko_mac_cfg.s.fifo_num = 0x1f;
|
|
|
|
pko_mac_cfg.s.min_pad_ena = pad_enable;
|
|
pko_mac_cfg.s.fcs_ena = fcs_enable;
|
|
pko_mac_cfg.s.fcs_sop_off = fcs_sop_off;
|
|
|
|
csr_wr_node(xi.node, CVMX_PKO_MACX_CFG(mac_num), pko_mac_cfg.u64);
|
|
|
|
pko_mac_cfg.s.fifo_num = fifo_num;
|
|
csr_wr_node(xi.node, CVMX_PKO_MACX_CFG(mac_num), pko_mac_cfg.u64);
|
|
|
|
if (debug)
|
|
debug("%s: PKO_MAC[%u]CFG=%#llx\n", __func__, mac_num,
|
|
(unsigned long long)csr_rd_node(xi.node, CVMX_PKO_MACX_CFG(mac_num)));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/** Set Descriptor Queue options
|
|
*
|
|
* The `min_pad` parameter must be in agreement with the interface-level
|
|
* padding option for all descriptor queues assigned to that particular
|
|
* interface/port.
|
|
*
|
|
* @param node on which to operate
|
|
* @param dq descriptor queue to set
|
|
* @param min_pad minimum padding to set for dq
|
|
*/
|
|
void cvmx_pko3_dq_options(unsigned int node, unsigned int dq, bool min_pad)
|
|
{
|
|
cvmx_pko_pdm_dqx_minpad_t reg;
|
|
|
|
dq &= (1 << 10) - 1;
|
|
reg.u64 = csr_rd_node(node, CVMX_PKO_PDM_DQX_MINPAD(dq));
|
|
reg.s.minpad = min_pad;
|
|
csr_wr_node(node, CVMX_PKO_PDM_DQX_MINPAD(dq), reg.u64);
|
|
}
|