Marek Vasut d339f16911 arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL ... Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code fine-tunes the behavior of the MMDC controller in order to improve the signal integrity and memory stability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>		2016-02-02 20:58:46 +01:00
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clock.h	imx: mx6: add clock api for lcdif	2015-11-12 17:40:53 +01:00
crm_regs.h	imx: mx6ul/sx: fix mmdc_ch0 clk calculation	2016-01-24 12:13:21 +01:00
gpio.h	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
imx-regs.h	imx: mx6: fix reg base address when runtime usage	2015-12-07 15:03:08 +01:00
iomux.h	pci: pcie_imx: Fix hang on mx6qp	2015-10-15 09:05:13 -04:00
mx6-ddr.h	arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL	2016-02-02 20:58:46 +01:00
mx6-pins.h	imx: mx6ul: Add pins IOMUX head file	2015-08-02 11:05:06 +02:00
mx6dl-ddr.h	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
mx6dl_pins.h	i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10	2014-07-10 15:23:56 +02:00
mx6q-ddr.h	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
mx6q_pins.h	imx6 SION bit has to be on for the pins that are used as ENET_REF_CLK	2014-02-19 10:57:25 +01:00
mx6sl-ddr.h	imx: mx6: ddr add dram io configuration and header file for i.MX6SL	2015-09-02 15:34:12 +02:00
mx6sl_pins.h	imx: mx6sl: Extend USDHC SD2 pins to support 8-wire use	2015-02-23 09:11:43 +01:00
mx6sx-ddr.h	mx6: Add support for the mx6solox variant	2014-07-10 15:29:16 +02:00
mx6sx_pins.h	imx: mx6sx enable SION for i2c pin mux	2015-05-19 15:13:24 +02:00
mx6ul-ddr.h	imx:mx6ul add dram spl configuration and header file	2015-08-02 11:05:09 +02:00
mx6ul_pins.h	imx: mx6ul: Add pins IOMUX head file	2015-08-02 11:05:06 +02:00
mxc_hdmi.h	Merge git://git.denx.de/u-boot-arm	2013-07-31 11:30:38 +02:00
sys_proto.h	imx-common: consolidate macros and prototypes into sys_proto.h	2015-09-02 15:29:14 +02:00