u-boot/board/freescale/mpc8313erdb
Simon Glass d30c7209df serial: Update NS16550_t and struct NS16550
Typedefs should not be used in U-Boot and structs should be lower case.
Update the code to use struct ns16550 consistently.

Put a header guard on the file while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05 12:24:40 -07:00
..
Kconfig mpc83xx: Make distinct MPC8313ERDB targets 2019-05-20 13:50:34 +02:00
MAINTAINERS MAINTAINERS: comment out blank M: field 2014-09-24 18:30:28 -04:00
Makefile SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
mpc8313erdb.c serial: Update NS16550_t and struct NS16550 2021-01-05 12:24:40 -07:00
README Use correct spelling of "U-Boot" 2016-02-06 12:00:59 +01:00
sdram.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00

Freescale MPC8313ERDB Board
-----------------------------------------

1.	Board Switches and Jumpers

	S3 is used to set CONFIG_SYS_RESET_SOURCE.

	To boot the image at 0xFE000000 in NOR flash, use these DIP
	switch settings for S3 S4:

	+------+	+------+
	|      |	| **** |
	| **** |	|      |
	+------+ ON	+------+ ON
	  4321		  4321
	(where the '*' indicates the position of the tab of the switch.)

	To boot the image at the beginning of NAND flash, use these
	DIP switch settings for S3 S4:

	+------+	+------+
	| *    |	|  *** |
	|  *** |	| *    |
	+------+ ON	+------+ ON
	  4321		  4321
	(where the '*' indicates the position of the tab of the switch.)

	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.

2.	Memory Map
	The memory map looks like this:

	0x0000_0000	0x07ff_ffff	DDR		 128M
	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
	0xe000_0000	0xe00f_ffff	IMMR		 1M
	0xe200_0000	0xe20f_ffff	PCI IO		 16M
	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
					LED Control (CS3)
	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M

	When booting from NAND, NAND flash is CS0 and NOR flash
	is CS1.

3.	Definitions

3.1	Explanation of NEW definitions in:

	include/configs/MPC8313ERDB.h

	CONFIG_MPC83xx		MPC83xx family
	CONFIG_MPC831x		MPC831x specific
	CONFIG_MPC8313ERDB	MPC8313ERDB board specific

4.	Compilation

	Assuming you're using BASH (or similar) as your shell:

	export CROSS_COMPILE=your-cross-compiler-prefix-
	make distclean
	make MPC8313ERDB_XXX_config
	(where XXX is:
	   33 - 33 MHz oscillator, boot from NOR flash
	   66 - 66 MHz oscillator, boot from NOR flash
	   NAND_33 - 33 MHz oscillator, boot from NAND flash
	   NAND_66 - 66 MHz oscillator, boot from NAND flash)
	make

5.	Downloading and Flashing Images

5.1	Reflash U-Boot Image using U-Boot

	NOR flash:

	=>run tftpflash

	You may want to try
	=>tftpboot $loadaddr $uboot
	first, to make sure that the TFTP load will succeed before it
	goes ahead and wipes out your current firmware.  And of course,
	have an alternate means of programming the flash available
	if the new U-Boot doesn't boot.

	NAND flash:

	=>tftpboot $loadaddr <filename>
	=>nand erase 0 0x80000
	=>nand write $loadaddr 0 0x80000

	...where 0x80000 is the filesize rounded up to
	the next 0x20000 increment.

5.2	Downloading and Booting Linux Kernel

	Ensure that all networking-related environment variables are set
	properly (including ipaddr, serverip, gatewayip (if needed),
	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
	fdtfile, and bootfile).

	Then, do one of the following, depending on whether you
	want an NFS root or a ramdisk root:

	=>run nfsboot
	or
	=>run ramboot

6	Notes

	The console baudrate for MPC8313ERDB is 115200bps.