mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
237 lines
5.6 KiB
C
237 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 NXP Semiconductors
|
|
* Author: Fabio Estevam <fabio.estevam@nxp.com>
|
|
*/
|
|
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/mx7-pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/gpio.h>
|
|
#include <asm/mach-imx/hab.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/mach-imx/mxc_i2c.h>
|
|
#include <asm/io.h>
|
|
#include <common.h>
|
|
#include <fsl_esdhc.h>
|
|
#include <i2c.h>
|
|
#include <mmc.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
#include <usb.h>
|
|
#include <netdev.h>
|
|
#include <power/pmic.h>
|
|
#include <power/pfuze3000_pmic.h>
|
|
#include "../freescale/common/pfuze.h"
|
|
#include <asm/setup.h>
|
|
#include <asm/bootm.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
|
|
PAD_CTL_HYS)
|
|
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
|
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
|
|
|
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
|
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
|
|
|
|
#ifdef CONFIG_SYS_I2C_MXC
|
|
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
|
/* I2C1 for PMIC */
|
|
static struct i2c_pads_info i2c_pad_info1 = {
|
|
.scl = {
|
|
.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
|
|
.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
|
|
.gp = IMX_GPIO_NR(4, 8),
|
|
},
|
|
.sda = {
|
|
.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
|
|
.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
|
|
.gp = IMX_GPIO_NR(4, 9),
|
|
},
|
|
};
|
|
#endif
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = PHYS_SDRAM_SIZE;
|
|
|
|
/* Subtract the defined OPTEE runtime firmware length */
|
|
#ifdef CONFIG_OPTEE_TZDRAM_SIZE
|
|
gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static iomux_v3_cfg_t const wdog_pads[] = {
|
|
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
|
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_iomux_uart(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
|
};
|
|
|
|
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
|
{USDHC3_BASE_ADDR},
|
|
};
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
/* Assume uSDHC3 emmc is always present */
|
|
return 1;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_POWER
|
|
#define I2C_PMIC 0
|
|
static struct pmic *pfuze;
|
|
int power_init_board(void)
|
|
{
|
|
int ret;
|
|
unsigned int reg, rev_id;
|
|
|
|
ret = power_pfuze3000_init(I2C_PMIC);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pfuze = pmic_get("PFUZE3000");
|
|
ret = pmic_probe(pfuze);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
|
|
pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
|
|
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
|
|
|
|
/* disable Low Power Mode during standby mode */
|
|
pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int ret = 0;
|
|
|
|
#ifdef CONFIG_USB_ETHER
|
|
ret = usb_eth_initialize(bis);
|
|
if (ret < 0)
|
|
printf("Error %d registering USB ether.\n", ret);
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#ifdef CONFIG_SYS_I2C_MXC
|
|
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
char *mode;
|
|
|
|
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
|
|
mode = "secure";
|
|
else
|
|
mode = "non-secure";
|
|
|
|
#ifdef CONFIG_OPTEE_TZDRAM_SIZE
|
|
unsigned long optee_start, optee_end;
|
|
|
|
optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
|
|
optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
|
|
|
|
printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
|
|
mode, optee_start, optee_end);
|
|
#else
|
|
printf("Board: WARP7 in %s mode\n", mode);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_usb_phy_mode(int port)
|
|
{
|
|
return USB_INIT_DEVICE;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
#ifdef CONFIG_SERIAL_TAG
|
|
struct tag_serialnr serialnr;
|
|
char serial_string[0x20];
|
|
#endif
|
|
|
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
|
|
set_wdog_reset(wdog);
|
|
|
|
/*
|
|
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
|
|
* since we use PMIC_PWRON to reset the board.
|
|
*/
|
|
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
|
|
|
#ifdef CONFIG_SECURE_BOOT
|
|
/* Determine HAB state */
|
|
env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
|
|
#else
|
|
env_set_ulong(HAB_ENABLED_ENVNAME, 0);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SERIAL_TAG
|
|
/* Set serial# standard environment variable based on OTP settings */
|
|
get_board_serial(&serialnr);
|
|
snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
|
|
serialnr.low, serialnr.high);
|
|
env_set("serial#", serial_string);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|