mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
135 lines
3 KiB
ArmAsm
135 lines
3 KiB
ArmAsm
/*
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* Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
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*
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* Copyright (C) 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/s3c6400.h>
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init:
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/* DMC1 base address 0x7e001000 */
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ldr r0, =ELFIN_DMC1_BASE
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ldr r1, =0x4
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str r1, [r0, #INDEX_DMC_MEMC_CMD]
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ldr r1, =DMC_DDR_REFRESH_PRD
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str r1, [r0, #INDEX_DMC_REFRESH_PRD]
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ldr r1, =DMC_DDR_CAS_LATENCY
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str r1, [r0, #INDEX_DMC_CAS_LATENCY]
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ldr r1, =DMC_DDR_t_DQSS
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str r1, [r0, #INDEX_DMC_T_DQSS]
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ldr r1, =DMC_DDR_t_MRD
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str r1, [r0, #INDEX_DMC_T_MRD]
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ldr r1, =DMC_DDR_t_RAS
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str r1, [r0, #INDEX_DMC_T_RAS]
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ldr r1, =DMC_DDR_t_RC
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str r1, [r0, #INDEX_DMC_T_RC]
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ldr r1, =DMC_DDR_t_RCD
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ldr r2, =DMC_DDR_schedule_RCD
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orr r1, r1, r2
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str r1, [r0, #INDEX_DMC_T_RCD]
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ldr r1, =DMC_DDR_t_RFC
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ldr r2, =DMC_DDR_schedule_RFC
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orr r1, r1, r2
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str r1, [r0, #INDEX_DMC_T_RFC]
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ldr r1, =DMC_DDR_t_RP
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ldr r2, =DMC_DDR_schedule_RP
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orr r1, r1, r2
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str r1, [r0, #INDEX_DMC_T_RP]
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ldr r1, =DMC_DDR_t_RRD
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str r1, [r0, #INDEX_DMC_T_RRD]
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ldr r1, =DMC_DDR_t_WR
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str r1, [r0, #INDEX_DMC_T_WR]
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ldr r1, =DMC_DDR_t_WTR
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str r1, [r0, #INDEX_DMC_T_WTR]
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ldr r1, =DMC_DDR_t_XP
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str r1, [r0, #INDEX_DMC_T_XP]
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ldr r1, =DMC_DDR_t_XSR
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str r1, [r0, #INDEX_DMC_T_XSR]
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ldr r1, =DMC_DDR_t_ESR
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str r1, [r0, #INDEX_DMC_T_ESR]
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ldr r1, =DMC1_MEM_CFG
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str r1, [r0, #INDEX_DMC_MEMORY_CFG]
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ldr r1, =DMC1_MEM_CFG2
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str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
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ldr r1, =DMC1_CHIP0_CFG
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str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
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ldr r1, =DMC_DDR_32_CFG
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str r1, [r0, #INDEX_DMC_USER_CONFIG]
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/* DMC0 DDR Chip 0 configuration direct command reg */
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ldr r1, =DMC_NOP0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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/* Precharge All */
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ldr r1, =DMC_PA0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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/* Auto Refresh 2 time */
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ldr r1, =DMC_AR0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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/* MRS */
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ldr r1, =DMC_mDDR_EMR0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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/* Mode Reg */
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ldr r1, =DMC_mDDR_MR0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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/* Enable DMC1 */
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mov r1, #0x0
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str r1, [r0, #INDEX_DMC_MEMC_CMD]
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check_dmc1_ready:
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ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
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mov r2, #0x3
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and r1, r1, r2
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cmp r1, #0x1
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bne check_dmc1_ready
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nop
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mov pc, lr
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.ltorg
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