mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
a3b02a1d49
As a prerequisite for adding a Meson GX MMC driver update the Meson GXBB / Odroid-C2 device tree in Uboot with the latest version from Linux. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
447 lines
11 KiB
Text
447 lines
11 KiB
Text
/*
|
|
* Copyright (c) 2016 Andreas Färber
|
|
*
|
|
* Copyright (c) 2016 BayLibre, SAS.
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
*
|
|
* Copyright (c) 2016 Endless Computers, Inc.
|
|
* Author: Carlo Caione <carlo@endlessm.com>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
/* 16 MiB reserved for Hardware ROM Firmware */
|
|
hwrom_reserved: hwrom@0 {
|
|
reg = <0x0 0x0 0x0 0x1000000>;
|
|
no-map;
|
|
};
|
|
|
|
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
|
|
secmon_reserved: secmon@10000000 {
|
|
reg = <0x0 0x10000000 0x0 0x200000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 0>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 0>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 0>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 0>;
|
|
};
|
|
|
|
l2: l2-cache0 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
xtal: xtal-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "xtal";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
firmware {
|
|
sm: secure-monitor {
|
|
compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
|
|
};
|
|
};
|
|
|
|
efuse: efuse {
|
|
compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
sn: sn@14 {
|
|
reg = <0x14 0x10>;
|
|
};
|
|
|
|
eth_mac: eth_mac@34 {
|
|
reg = <0x34 0x10>;
|
|
};
|
|
|
|
bid: bid@46 {
|
|
reg = <0x46 0x30>;
|
|
};
|
|
};
|
|
|
|
scpi {
|
|
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
|
|
mboxes = <&mailbox 1 &mailbox 2>;
|
|
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
|
|
|
|
scpi_clocks: clocks {
|
|
compatible = "arm,scpi-clocks";
|
|
|
|
scpi_dvfs: scpi_clocks@0 {
|
|
compatible = "arm,scpi-dvfs-clocks";
|
|
#clock-cells = <1>;
|
|
clock-indices = <0>;
|
|
clock-output-names = "vcpu";
|
|
};
|
|
};
|
|
|
|
scpi_sensors: sensors {
|
|
compatible = "arm,scpi-sensors";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
cbus: cbus@c1100000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xc1100000 0x0 0x100000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
|
|
|
|
reset: reset-controller@4404 {
|
|
compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
|
|
reg = <0x0 0x04404 0x0 0x20>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
uart_A: serial@84c0 {
|
|
compatible = "amlogic,meson-uart";
|
|
reg = <0x0 0x84c0 0x0 0x14>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_B: serial@84dc {
|
|
compatible = "amlogic,meson-uart";
|
|
reg = <0x0 0x84dc 0x0 0x14>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_A: i2c@8500 {
|
|
compatible = "amlogic,meson-gxbb-i2c";
|
|
reg = <0x0 0x08500 0x0 0x20>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ab: pwm@8550 {
|
|
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
|
reg = <0x0 0x08550 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_cd: pwm@8650 {
|
|
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
|
reg = <0x0 0x08650 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ef: pwm@86c0 {
|
|
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
|
reg = <0x0 0x086c0 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_C: serial@8700 {
|
|
compatible = "amlogic,meson-uart";
|
|
reg = <0x0 0x8700 0x0 0x14>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_B: i2c@87c0 {
|
|
compatible = "amlogic,meson-gxbb-i2c";
|
|
reg = <0x0 0x087c0 0x0 0x20>;
|
|
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_C: i2c@87e0 {
|
|
compatible = "amlogic,meson-gxbb-i2c";
|
|
reg = <0x0 0x087e0 0x0 0x20>;
|
|
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog@98d0 {
|
|
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
|
|
reg = <0x0 0x098d0 0x0 0x10>;
|
|
clocks = <&xtal>;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@c4301000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x0 0xc4301000 0 0x1000>,
|
|
<0x0 0xc4302000 0 0x2000>,
|
|
<0x0 0xc4304000 0 0x2000>,
|
|
<0x0 0xc4306000 0 0x2000>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
};
|
|
|
|
sram: sram@c8000000 {
|
|
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
|
|
reg = <0x0 0xc8000000 0x0 0x14000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0xc8000000 0x14000>;
|
|
|
|
cpu_scp_lpri: scp-shmem@0 {
|
|
compatible = "amlogic,meson-gxbb-scp-shmem";
|
|
reg = <0x13000 0x400>;
|
|
};
|
|
|
|
cpu_scp_hpri: scp-shmem@200 {
|
|
compatible = "amlogic,meson-gxbb-scp-shmem";
|
|
reg = <0x13400 0x400>;
|
|
};
|
|
};
|
|
|
|
aobus: aobus@c8100000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xc8100000 0x0 0x100000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
|
|
|
|
uart_AO: serial@4c0 {
|
|
compatible = "amlogic,meson-uart";
|
|
reg = <0x0 0x004c0 0x0 0x14>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_AO_B: serial@4e0 {
|
|
compatible = "amlogic,meson-uart";
|
|
reg = <0x0 0x004e0 0x0 0x14>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ir: ir@580 {
|
|
compatible = "amlogic,meson-gxbb-ir";
|
|
reg = <0x0 0x00580 0x0 0x40>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
periphs: periphs@c8834000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xc8834000 0x0 0x2000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
|
|
|
|
rng {
|
|
compatible = "amlogic,meson-rng";
|
|
reg = <0x0 0x0 0x0 0x4>;
|
|
};
|
|
};
|
|
|
|
|
|
hiubus: hiubus@c883c000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xc883c000 0x0 0x2000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
|
|
|
|
mailbox: mailbox@404 {
|
|
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
|
|
reg = <0 0x404 0 0x4c>;
|
|
interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
|
|
<0 209 IRQ_TYPE_EDGE_RISING>,
|
|
<0 210 IRQ_TYPE_EDGE_RISING>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
};
|
|
|
|
ethmac: ethernet@c9410000 {
|
|
compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
|
|
reg = <0x0 0xc9410000 0x0 0x10000
|
|
0x0 0xc8834540 0x0 0x4>;
|
|
interrupts = <0 8 1>;
|
|
interrupt-names = "macirq";
|
|
phy-mode = "rgmii";
|
|
status = "disabled";
|
|
};
|
|
|
|
apb: apb@d0000000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xd0000000 0x0 0x200000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
|
|
|
|
sd_emmc_a: mmc@70000 {
|
|
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
|
|
reg = <0x0 0x70000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd_emmc_b: mmc@72000 {
|
|
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
|
|
reg = <0x0 0x72000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd_emmc_c: mmc@74000 {
|
|
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
|
|
reg = <0x0 0x74000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
vpu: vpu@d0100000 {
|
|
compatible = "amlogic,meson-gx-vpu";
|
|
reg = <0x0 0xd0100000 0x0 0x100000>,
|
|
<0x0 0xc883c000 0x0 0x1000>,
|
|
<0x0 0xc8838000 0x0 0x1000>;
|
|
reg-names = "vpu", "hhi", "dmc";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* CVBS VDAC output port */
|
|
cvbs_vdac_port: port@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|