mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
a7551cf05d
Add the basic a72 dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
117 lines
2.9 KiB
Text
117 lines
2.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
|
|
*
|
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
&cbass_mcu_wakeup {
|
|
dmsc: dmsc@44083000 {
|
|
compatible = "ti,k2g-sci";
|
|
ti,host-id = <12>;
|
|
|
|
mbox-names = "rx", "tx";
|
|
|
|
mboxes= <&secure_proxy_main 11>,
|
|
<&secure_proxy_main 13>;
|
|
|
|
reg-names = "debug_messages";
|
|
reg = <0x00 0x44083000 0x0 0x1000>;
|
|
|
|
k3_pds: power-controller {
|
|
compatible = "ti,sci-pm-domain";
|
|
#power-domain-cells = <2>;
|
|
};
|
|
|
|
k3_clks: clocks {
|
|
compatible = "ti,k2g-sci-clk";
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
k3_reset: reset-controller {
|
|
compatible = "ti,sci-reset";
|
|
#reset-cells = <2>;
|
|
};
|
|
};
|
|
|
|
chipid: chipid@43000014 {
|
|
compatible = "ti,am654-chipid";
|
|
reg = <0x0 0x43000014 0x0 0x4>;
|
|
};
|
|
|
|
wkup_pmx0: pinmux@4301c000 {
|
|
compatible = "pinctrl-single";
|
|
/* Proxy 0 addressing */
|
|
reg = <0x00 0x4301c000 0x00 0x178>;
|
|
#pinctrl-cells = <1>;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0xffffffff>;
|
|
};
|
|
|
|
mcu_ram: sram@41c00000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x00 0x41c00000 0x00 0x100000>;
|
|
ranges = <0x0 0x00 0x41c00000 0x100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
wkup_uart0: serial@42300000 {
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
reg = <0x00 0x42300000 0x00 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
current-speed = <115200>;
|
|
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 287 2>;
|
|
clock-names = "fclk";
|
|
};
|
|
|
|
wkup_i2c0: i2c@42120000 {
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
|
reg = <0x0 0x42120000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "fck";
|
|
clocks = <&k3_clks 197 1>;
|
|
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
|
|
};
|
|
|
|
mcu_uart0: serial@40a00000 {
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
reg = <0x00 0x40a00000 0x00 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <96000000>;
|
|
current-speed = <115200>;
|
|
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 149 2>;
|
|
clock-names = "fclk";
|
|
};
|
|
|
|
mcu_i2c0: i2c@40b00000 {
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
|
reg = <0x0 0x40b00000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "fck";
|
|
clocks = <&k3_clks 194 1>;
|
|
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
|
|
};
|
|
|
|
mcu_i2c1: i2c@40b10000 {
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
|
reg = <0x0 0x40b10000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "fck";
|
|
clocks = <&k3_clks 195 1>;
|
|
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
|
};
|
|
};
|