mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 10:52:09 +00:00
dea0f1a27f
Sync the serial nodes of the LX2160A based boards with their representation in Linux. We also imported the clockgen and sysclk nodes which are dependencies. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
148 lines
2.5 KiB
Text
148 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* NXP LX2160ARDB device tree source
|
|
*
|
|
* Author: Priyanka Jain <priyanka.jain@nxp.com>
|
|
* Sriram Dash <sriram.dash@nxp.com>
|
|
*
|
|
* Copyright 2018, 2023 NXP
|
|
*
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "fsl-lx2160a.dtsi"
|
|
|
|
/ {
|
|
model = "NXP Layerscape LX2160ARDB Board";
|
|
compatible = "fsl,lx2160ardb", "fsl,lx2160a";
|
|
aliases {
|
|
spi0 = &fspi;
|
|
serial0 = &uart0;
|
|
};
|
|
};
|
|
|
|
&dpmac3 {
|
|
status = "okay";
|
|
phy-handle = <&aquantia_phy1>;
|
|
phy-connection-type = "usxgmii";
|
|
};
|
|
|
|
&dpmac4 {
|
|
status = "okay";
|
|
phy-handle = <&aquantia_phy2>;
|
|
phy-connection-type = "usxgmii";
|
|
};
|
|
|
|
&dpmac17 {
|
|
status = "okay";
|
|
phy-handle = <&rgmii_phy1>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
&dpmac18 {
|
|
status = "okay";
|
|
phy-handle = <&rgmii_phy2>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
&emdio1 {
|
|
status = "okay";
|
|
rgmii_phy1: ethernet-phy@1 {
|
|
/* AR8035 PHY - "compatible" property not strictly needed */
|
|
compatible = "ethernet-phy-id004d.d072";
|
|
reg = <0x1>;
|
|
/* Poll mode - no "interrupts" property defined */
|
|
};
|
|
rgmii_phy2: ethernet-phy@2 {
|
|
/* AR8035 PHY - "compatible" property not strictly needed */
|
|
compatible = "ethernet-phy-id004d.d072";
|
|
reg = <0x2>;
|
|
/* Poll mode - no "interrupts" property defined */
|
|
};
|
|
aquantia_phy1: ethernet-phy@4 {
|
|
/* AQR107 PHY - "compatible" property not strictly needed */
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x4>;
|
|
};
|
|
aquantia_phy2: ethernet-phy@5 {
|
|
/* AQR107 PHY - "compatible" property not strictly needed */
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x5>;
|
|
};
|
|
};
|
|
|
|
&esdhc0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&esdhc1 {
|
|
status = "okay";
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
bus-width = <8>;
|
|
};
|
|
|
|
&fspi {
|
|
status = "okay";
|
|
|
|
mt35xu512aba0: flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "jedec,spi-nor";
|
|
spi-max-frequency = <50000000>;
|
|
reg = <0>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-tx-bus-width = <1>;
|
|
};
|
|
|
|
mt35xu512aba1: flash@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "jedec,spi-nor";
|
|
spi-max-frequency = <50000000>;
|
|
reg = <1>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-tx-bus-width = <1>;
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
bootph-all;
|
|
};
|
|
|
|
&i2c4 {
|
|
status = "okay";
|
|
|
|
rtc@51 {
|
|
compatible = "nxp,pcf2129";
|
|
reg = <0x51>;
|
|
};
|
|
};
|
|
|
|
&sata0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|