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d25ba89e8b
On NXP LPC32xx platform for non-SPL builds the change adds standard (NS16550) and high-speed UARTs to driver model. Due to specific of DM NS16550 device description UART clock can not be got in runtime and by default it is set to 13MHz, if board PERIPH_CLK is different, this should be specified in board configuration file. For SPL builds HSUARTs are disabled and non-DM NS16550 driver is compiled, if needed. The change also updates default configs of devkit3250 and work_92105 boards to reflect updates in platform files. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <dm/platform_data/lpc32xx_hsuart.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/uart.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
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static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
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void lpc32xx_uart_init(unsigned int uart_id)
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{
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if (uart_id < 1 || uart_id > 7)
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return;
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/* Disable loopback mode, if it is set by S1L bootloader */
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clrbits_le32(&ctrl->loop,
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UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
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if (uart_id < 3 || uart_id > 6)
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return;
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/* Enable UART system clock */
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setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
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/* Set UART into autoclock mode */
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clrsetbits_le32(&ctrl->clkmode,
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UART_CLKMODE_MASK(uart_id),
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UART_CLKMODE_AUTO(uart_id));
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/* Bypass pre-divider of UART clock */
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writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
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&clk->u3clk + (uart_id - 3));
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}
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#if !CONFIG_IS_ENABLED(OF_CONTROL) && !defined(CONFIG_SPL_BUILD)
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static const struct ns16550_platdata lpc32xx_uart[] = {
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{ UART3_BASE, 2, CONFIG_SYS_NS16550_CLK },
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{ UART4_BASE, 2, CONFIG_SYS_NS16550_CLK },
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{ UART5_BASE, 2, CONFIG_SYS_NS16550_CLK },
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{ UART6_BASE, 2, CONFIG_SYS_NS16550_CLK },
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};
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#if defined(CONFIG_LPC32XX_HSUART)
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static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
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{ HS_UART1_BASE, },
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{ HS_UART2_BASE, },
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{ HS_UART7_BASE, },
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};
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#endif
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U_BOOT_DEVICES(lpc32xx_uarts) = {
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#if defined(CONFIG_LPC32XX_HSUART)
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{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
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{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
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#endif
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{ "ns16550_serial", &lpc32xx_uart[0], },
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{ "ns16550_serial", &lpc32xx_uart[1], },
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{ "ns16550_serial", &lpc32xx_uart[2], },
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{ "ns16550_serial", &lpc32xx_uart[3], },
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#if defined(CONFIG_LPC32XX_HSUART)
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{ "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
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#endif
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};
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#endif
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void lpc32xx_dma_init(void)
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{
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/* Enable DMA interface */
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writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
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}
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void lpc32xx_mac_init(void)
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{
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/* Enable MAC interface */
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writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
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#if defined(CONFIG_RMII)
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| CLK_MAC_RMII,
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#else
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| CLK_MAC_MII,
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#endif
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&clk->macclk_ctrl);
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}
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void lpc32xx_mlc_nand_init(void)
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{
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/* Enable NAND interface */
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writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
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}
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void lpc32xx_slc_nand_init(void)
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{
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/* Enable SLC NAND interface */
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writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
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}
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void lpc32xx_usb_init(void)
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{
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/* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
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clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
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}
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void lpc32xx_i2c_init(unsigned int devnum)
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{
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/* Enable I2C interface */
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uint32_t ctrl = readl(&clk->i2cclk_ctrl);
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if (devnum == 1)
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ctrl |= CLK_I2C1_ENABLE;
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if (devnum == 2)
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ctrl |= CLK_I2C2_ENABLE;
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writel(ctrl, &clk->i2cclk_ctrl);
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}
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U_BOOT_DEVICE(lpc32xx_gpios) = {
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.name = "gpio_lpc32xx"
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};
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/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
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#define P_MUX_SET_SSP0 0x1600
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void lpc32xx_ssp_init(void)
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{
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/* Enable SSP0 interface */
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writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
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/* Mux SSP0 pins */
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writel(P_MUX_SET_SSP0, &mux->p_mux_set);
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}
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