mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
e6fa0dcc6f
Long are gone the times TF-A couldn't handle the FDT passed by U-Boot.
Specifically, since commit e7b586987c0a ("rockchip: don't crash if we
get an FDT we can't parse") in TF-A, failure to parse the FDT will use
the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two
years ago.
New boards should likely have this option disabled or explicitly enable
it in their respective defconfig.
Because existing boards might depend on a TF-A version that predates
v2.4, let's just enable this option in all RK3399 defconfigs.
Maintainers of each board can decide for themselves if they would prefer
to disable this option and allow U-Boot to pass the DT to TF-A.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
100 lines
2.6 KiB
Text
100 lines
2.6 KiB
Text
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00200000
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CONFIG_SPL_GPIO=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
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CONFIG_ENV_SIZE=0x8000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_ENV_SECT_SIZE=0x1000
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CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_TARGET_ROC_PC_RK3399=y
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CONFIG_SPL_STACK=0x400000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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# CONFIG_ANDROID_BOOT_IMAGE is not set
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x2e000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x400000
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CONFIG_SPL_BSS_MAX_SIZE=0x2000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_TPL=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIME=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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# CONFIG_RAM_ROCKCHIP_DEBUG is not set
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CONFIG_RAM_ROCKCHIP_LPDDR4=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_ROCKCHIP_SPI=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_USB_GADGET=y
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CONFIG_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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