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9751ee0990
Renesas SH7763 has 2 channel Ethernet device. This is 10/100/1000 Base support. But this patch check 10/100 Base only. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
446 lines
13 KiB
C
446 lines
13 KiB
C
/*
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* sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <asm/types.h>
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#define SHETHER_NAME "sh_eth"
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/* Malloc returns addresses in the P1 area (cacheable). However we need to
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use area P2 (non-cacheable) */
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#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
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/* The ethernet controller needs to use physical addresses */
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#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
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/* Number of supported ports */
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#define MAX_PORT_NUM 2
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/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
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buffers must be a multiple of 32 bytes */
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#define MAX_BUF_SIZE (48 * 32)
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/* The number of tx descriptors must be large enough to point to 5 or more
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frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
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We use one descriptor per frame */
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#define NUM_TX_DESC 8
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/* The size of the tx descriptor is determined by how much padding is used.
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4, 20, or 52 bytes of padding can be used */
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#define TX_DESC_PADDING 4
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#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
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/* Tx descriptor. We always use 4 bytes of padding */
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struct tx_desc_s {
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volatile u32 td0;
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u32 td1;
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u32 td2; /* Buffer start */
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u32 padding;
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};
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/* There is no limitation in the number of rx descriptors */
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#define NUM_RX_DESC 8
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/* The size of the rx descriptor is determined by how much padding is used.
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4, 20, or 52 bytes of padding can be used */
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#define RX_DESC_PADDING 4
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#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
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/* Rx descriptor. We always use 4 bytes of padding */
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struct rx_desc_s {
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volatile u32 rd0;
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volatile u32 rd1;
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u32 rd2; /* Buffer start */
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u32 padding;
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};
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struct port_info_s {
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struct tx_desc_s *tx_desc_malloc;
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struct tx_desc_s *tx_desc_base;
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struct tx_desc_s *tx_desc_cur;
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struct rx_desc_s *rx_desc_malloc;
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struct rx_desc_s *rx_desc_base;
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struct rx_desc_s *rx_desc_cur;
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u8 *rx_buf_malloc;
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u8 *rx_buf_base;
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u8 mac_addr[6];
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u8 phy_addr;
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};
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struct dev_info_s {
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int port;
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struct port_info_s port_info[MAX_PORT_NUM];
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};
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/* Register Address */
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#define BASE_IO_ADDR 0xfee00000
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#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
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#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
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#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
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#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
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#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
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#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
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#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
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#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
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#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
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#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
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#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
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#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
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#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
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#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
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#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
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#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
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#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
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#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
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#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
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#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
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#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
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#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
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#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
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#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
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#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
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#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
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#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
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#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
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#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
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#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
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#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
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/*
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* Register's bits
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* Copy from Linux driver source code
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*/
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#ifdef CONFIG_CPU_SH7763
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/* EDSR */
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enum EDSR_BIT {
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EDSR_ENT = 0x01, EDSR_ENR = 0x02,
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};
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#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
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#endif
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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#ifdef CONFIG_CPU_SH7763
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EDMR_SRST = 0x03,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#else /* CONFIG_CPU_SH7763 */
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EDMR_SRST = 0x01,
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#endif
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};
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/* RFLR */
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#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
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/* EDTRR */
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enum DMAC_T_BIT {
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#ifdef CONFIG_CPU_SH7763
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EDTRR_TRNS = 0x03,
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#else
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EDTRR_TRNS = 0x01,
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#endif
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};
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/* GECMR */
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enum GECMR_BIT {
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GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00,
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};
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/* EDRRR*/
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enum EDRRR_R_BIT {
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EDRRR_R = 0x01,
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};
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/* TPAUSER */
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enum TPAUSER_BIT {
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TPAUSER_TPAUSE = 0x0000ffff,
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TPAUSER_UNLIMITED = 0,
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};
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/* BCFR */
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enum BCFR_BIT {
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BCFR_RPAUSE = 0x0000ffff,
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BCFR_UNLIMITED = 0,
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};
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/* PIR */
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enum PIR_BIT {
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PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
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};
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/* PSR */
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enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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#ifndef CONFIG_CPU_SH7763
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EESR_TWB = 0x40000000,
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#else
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EESR_TWB = 0xC0000000,
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EESR_TC1 = 0x20000000,
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EESR_TUC = 0x10000000,
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EESR_ROC = 0x80000000,
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#endif
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
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#ifndef CONFIG_CPU_SH7763
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EESR_ADE = 0x00800000,
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#endif
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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#ifndef CONFIG_CPU_SH7763
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EESR_CND = 0x00000800,
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#endif
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EESR_DLC = 0x00000400,
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EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
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EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
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EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
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rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
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EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
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};
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#ifdef CONFIG_CPU_SH7763
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# define TX_CHECK (EESR_TC1 | EESR_FTC)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
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#else
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# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
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#endif
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/* EESIPR */
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enum DMAC_IM_BIT {
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DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
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DMAC_M_RABT = 0x02000000,
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DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
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DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
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DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
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DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
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DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
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DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
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DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
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DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
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DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
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DMAC_M_RINT1 = 0x00000001,
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};
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/* Receive descriptor bit */
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enum RD_STS_BIT {
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RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
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RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
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RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
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RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
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RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
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RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
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RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
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RD_RFS1 = 0x00000001,
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};
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#define RDF1ST RD_RFP1
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#define RDFEND RD_RFP0
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#define RD_RFP (RD_RFP1|RD_RFP0)
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/* RDFFR*/
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enum RDFFR_BIT {
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RDFFR_RDLF = 0x01,
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};
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/* FCFTR */
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enum FCFTR_BIT {
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FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
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FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
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FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
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};
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#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
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#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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#ifdef CONFIG_CPU_SH7763
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TD_TACT = 0x80000000,
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#else
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TD_TACT = 0x7fffffff,
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#endif
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TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
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TD_TFP0 = 0x10000000,
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};
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#define TDF1ST TD_TFP1
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#define TDFEND TD_TFP0
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#define TD_TFP (TD_TFP1|TD_TFP0)
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/* RMCR */
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enum RECV_RST_BIT { RMCR_RST = 0x01, };
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/* ECMR */
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enum FELIC_MODE_BIT {
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#ifdef CONFIG_CPU_SH7763
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ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
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ECMR_RZPF = 0x00100000,
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#endif
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ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
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ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
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ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
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ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
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ECMR_PRM = 0x00000001,
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};
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#ifdef CONFIG_CPU_SH7763
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
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ECMR_TXF | ECMR_MCT)
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#else
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#endif
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/* ECSR */
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enum ECSR_STATUS_BIT {
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#ifndef CONFIG_CPU_SH7763
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ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
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#endif
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ECSR_LCHNG = 0x04,
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ECSR_MPD = 0x02, ECSR_ICD = 0x01,
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};
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#ifdef CONFIG_CPU_SH7763
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# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
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#else
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# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
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ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
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#endif
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/* ECSIPR */
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enum ECSIPR_STATUS_MASK_BIT {
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#ifndef CONFIG_CPU_SH7763
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ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
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#endif
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ECSIPR_LCHNGIP = 0x04,
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ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
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};
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#ifdef CONFIG_CPU_SH7763
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# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
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#else
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# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
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ECSIPR_ICDIP | ECSIPR_MPDIP)
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#endif
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/* APR */
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enum APR_BIT {
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APR_AP = 0x00000004,
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};
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/* MPR */
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enum MPR_BIT {
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MPR_MP = 0x00000006,
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};
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/* TRSCER */
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enum DESC_I_BIT {
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DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
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DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
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DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
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DESC_I_RINT1 = 0x0001,
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};
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/* RPADIR */
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enum RPADIR_BIT {
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RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
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RPADIR_PADR = 0x0003f,
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};
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#ifdef CONFIG_CPU_SH7763
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# define RPADIR_INIT (0x00)
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#else
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# define RPADIR_INIT (RPADIR_PADS1)
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#endif
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/* FDR */
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enum FIFO_SIZE_BIT {
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FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
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};
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enum PHY_OFFSETS {
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PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
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PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
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PHY_16 = 16,
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};
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/* PHY_CTRL */
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enum PHY_CTRL_BIT {
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PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
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PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
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PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
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};
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#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
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/* PHY_STAT */
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enum PHY_STAT_BIT {
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PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
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PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
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|
PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
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PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
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|
};
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|
|
|
/* PHY_ANA */
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|
enum PHY_ANA_BIT {
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PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
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|
PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
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|
PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
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|
PHY_A_SEL = 0x001e,
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|
PHY_A_EXT = 0x0001,
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|
};
|
|
|
|
/* PHY_ANL */
|
|
enum PHY_ANL_BIT {
|
|
PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
|
|
PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
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|
PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
|
|
PHY_L_SEL = 0x001f,
|
|
};
|
|
|
|
/* PHY_ANE */
|
|
enum PHY_ANE_BIT {
|
|
PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
|
|
PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
|
|
};
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|
|
|
/* DM9161 */
|
|
enum PHY_16_BIT {
|
|
PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
|
|
PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
|
|
PHY_16_TXselect = 0x0400,
|
|
PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
|
|
PHY_16_Force100LNK = 0x0080,
|
|
PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
|
|
PHY_16_RPDCTR_EN = 0x0010,
|
|
PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
|
|
PHY_16_Sleepmode = 0x0002,
|
|
PHY_16_RemoteLoopOut = 0x0001,
|
|
};
|