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65c575506d
The atmel at91sam9x5 series spi has feature to avoid receive overren Using the patch to enable it Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
/*
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* Register definitions for the Atmel AT32/AT91 SPI Controller
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*/
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/* Register offsets */
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#define ATMEL_SPI_CR 0x0000
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#define ATMEL_SPI_MR 0x0004
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#define ATMEL_SPI_RDR 0x0008
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#define ATMEL_SPI_TDR 0x000c
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#define ATMEL_SPI_SR 0x0010
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#define ATMEL_SPI_IER 0x0014
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#define ATMEL_SPI_IDR 0x0018
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#define ATMEL_SPI_IMR 0x001c
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#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x))
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#define ATMEL_SPI_VERSION 0x00fc
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/* Bits in CR */
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#define ATMEL_SPI_CR_SPIEN (1 << 0)
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#define ATMEL_SPI_CR_SPIDIS (1 << 1)
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#define ATMEL_SPI_CR_SWRST (1 << 7)
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#define ATMEL_SPI_CR_LASTXFER (1 << 24)
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/* Bits in MR */
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#define ATMEL_SPI_MR_MSTR (1 << 0)
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#define ATMEL_SPI_MR_PS (1 << 1)
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#define ATMEL_SPI_MR_PCSDEC (1 << 2)
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#define ATMEL_SPI_MR_FDIV (1 << 3)
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#define ATMEL_SPI_MR_MODFDIS (1 << 4)
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#define ATMEL_SPI_MR_WDRBT (1 << 5)
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#define ATMEL_SPI_MR_LLB (1 << 7)
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#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
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#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
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/* Bits in RDR */
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#define ATMEL_SPI_RDR_RD(x) (x)
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#define ATMEL_SPI_RDR_PCS(x) ((x) << 16)
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/* Bits in TDR */
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#define ATMEL_SPI_TDR_TD(x) (x)
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#define ATMEL_SPI_TDR_PCS(x) ((x) << 16)
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#define ATMEL_SPI_TDR_LASTXFER (1 << 24)
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/* Bits in SR/IER/IDR/IMR */
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#define ATMEL_SPI_SR_RDRF (1 << 0)
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#define ATMEL_SPI_SR_TDRE (1 << 1)
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#define ATMEL_SPI_SR_MODF (1 << 2)
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#define ATMEL_SPI_SR_OVRES (1 << 3)
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#define ATMEL_SPI_SR_ENDRX (1 << 4)
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#define ATMEL_SPI_SR_ENDTX (1 << 5)
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#define ATMEL_SPI_SR_RXBUFF (1 << 6)
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#define ATMEL_SPI_SR_TXBUFE (1 << 7)
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#define ATMEL_SPI_SR_NSSR (1 << 8)
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#define ATMEL_SPI_SR_TXEMPTY (1 << 9)
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#define ATMEL_SPI_SR_SPIENS (1 << 16)
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/* Bits in CSRx */
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#define ATMEL_SPI_CSRx_CPOL (1 << 0)
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#define ATMEL_SPI_CSRx_NCPHA (1 << 1)
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#define ATMEL_SPI_CSRx_CSAAT (1 << 3)
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#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
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#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
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#define ATMEL_SPI_CSRx_SCBR_MAX 0xff
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#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16)
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#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)
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/* Bits in VERSION */
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#define ATMEL_SPI_VERSION_REV(x) ((x) << 0)
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#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16)
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/* Constants for CSRx:BITS */
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#define ATMEL_SPI_BITS_8 0
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#define ATMEL_SPI_BITS_9 1
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#define ATMEL_SPI_BITS_10 2
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#define ATMEL_SPI_BITS_11 3
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#define ATMEL_SPI_BITS_12 4
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#define ATMEL_SPI_BITS_13 5
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#define ATMEL_SPI_BITS_14 6
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#define ATMEL_SPI_BITS_15 7
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#define ATMEL_SPI_BITS_16 8
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struct atmel_spi_slave {
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struct spi_slave slave;
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void *regs;
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u32 mr;
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};
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static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct atmel_spi_slave, slave);
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}
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/* Register access macros */
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#define spi_readl(as, reg) \
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readl(as->regs + ATMEL_SPI_##reg)
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#define spi_writel(as, reg, value) \
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writel(value, as->regs + ATMEL_SPI_##reg)
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