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47deb4b4a9
Per new requirement, change default core frequency from previous 1400MHz to 1200MHz to save power. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
8 lines
288 B
INI
8 lines
288 B
INI
#PBL preamble and RCW header for T1023RDB
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aa55aa55 010e0100
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#SerDes Protocol: 0x77
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#Default Core=1200MHz, DDR=1600MT/s with single source clock
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0810000c 00000000 00000000 00000000
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3b800003 00000012 e8104000 21000000
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00000000 00000000 00000000 00022800
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00000130 04020200 00000000 00000006
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