mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
39edfaa758
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
73 lines
1.8 KiB
PHP
73 lines
1.8 KiB
PHP
{
|
|
{
|
|
{
|
|
.rank = 0x1,
|
|
.col = 0xC,
|
|
.bk = 0x3,
|
|
.bw = 0x1,
|
|
.dbw = 0x0,
|
|
.row_3_4 = 0x0,
|
|
.cs0_row = 0xF,
|
|
.cs1_row = 0xF,
|
|
.cs0_high16bit_row = 0xF,
|
|
.cs1_high16bit_row = 0xF,
|
|
.ddrconfig = 0,
|
|
},
|
|
{
|
|
{0x2b0c070a},
|
|
{0x08020303},
|
|
{0x00000002},
|
|
{0x00001111},
|
|
{0x0000000c},
|
|
{0x00000219},
|
|
0x000000ff
|
|
}
|
|
},
|
|
{
|
|
.ddr_freq = 333,
|
|
.dramtype = LPDDR2,
|
|
.num_channels = 1,
|
|
.stride = 0,
|
|
.odt = 0,
|
|
},
|
|
{
|
|
{
|
|
{0x00000000, 0x41041004}, /* MSTR */
|
|
{0x00000064, 0x00140023}, /* RFSHTMG */
|
|
{0x000000d0, 0x00220002}, /* INIT0 */
|
|
{0x000000d4, 0x00010000}, /* INIT1 */
|
|
{0x000000d8, 0x00000703}, /* INIT2 */
|
|
{0x000000dc, 0x00630005}, /* INIT3 */
|
|
{0x000000e0, 0x00010000}, /* INIT4 */
|
|
{0x000000e4, 0x00070003}, /* INIT5 */
|
|
{0x000000f4, 0x000f012f}, /* RANKCTL */
|
|
{0x00000100, 0x07090b07}, /* DRAMTMG0 */
|
|
{0x00000104, 0x0002010b}, /* DRAMTMG1 */
|
|
{0x00000108, 0x02040506}, /* DRAMTMG2 */
|
|
{0x0000010c, 0x00303000}, /* DRAMTMG3 */
|
|
{0x00000110, 0x04010204}, /* DRAMTMG4 */
|
|
{0x00000114, 0x01010303}, /* DRAMTMG5 */
|
|
{0x00000118, 0x02020003}, /* DRAMTMG6 */
|
|
{0x00000120, 0x00000303}, /* DRAMTMG8 */
|
|
{0x00000138, 0x00000025}, /* DRAMTMG14 */
|
|
{0x00000180, 0x003c000f}, /* ZQCTL0 */
|
|
{0x00000184, 0x00900000}, /* ZQCTL1 */
|
|
{0x00000190, 0x07020001}, /* DFITMG0 */
|
|
{0x00000198, 0x07000101}, /* DFILPCFG0 */
|
|
{0x000001a0, 0xc0400003}, /* DFIUPD0 */
|
|
{0x00000240, 0x07030718}, /* ODTCFG */
|
|
{0x00000250, 0x00001f00}, /* SCHED */
|
|
{0x00000490, 0x00000001}, /* PCTRL_0 */
|
|
{0xffffffff, 0xffffffff}
|
|
}
|
|
},
|
|
{
|
|
{
|
|
{0x00000004, 0x00000009}, /* PHYREG01 */
|
|
{0x00000028, 0x00000007}, /* PHYREG0A */
|
|
{0x0000002c, 0x00000000}, /* PHYREG0B */
|
|
{0x00000030, 0x00000004}, /* PHYREG0C */
|
|
{0xffffffff, 0xffffffff}
|
|
}
|
|
}
|
|
},
|