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https://github.com/AsahiLinux/u-boot
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d1d8814458
The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
201 lines
3.5 KiB
Text
201 lines
3.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mt7628a-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mti,mips24KEc";
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device_type = "cpu";
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reg = <0>;
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};
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};
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resetc: reset-controller {
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compatible = "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus@10000000 {
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compatible = "palmbus", "simple-bus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: system-controller@0 {
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compatible = "ralink,mt7620a-sysc", "syscon";
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reg = <0x0 0x100>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&sysc>;
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offset = <0x34>;
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mask = <0x1>;
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};
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watchdog: watchdog@100 {
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compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
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reg = <0x100 0x30>;
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resets = <&resetc 8>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <24>;
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};
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intc: interrupt-controller@200 {
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compatible = "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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resets = <&resetc 9>;
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reset-names = "intc";
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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};
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memory-controller@300 {
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compatible = "ralink,mt7620a-memc";
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reg = <0x300 0x100>;
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};
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gpio@600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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reg = <0x600 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio0: bank@0 {
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reg = <0>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: bank@1 {
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reg = <1>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: bank@2 {
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reg = <2>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi0: spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <200000000>;
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};
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uart0: uartlite@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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clock-frequency = <40000000>;
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resets = <&resetc 12>;
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reset-names = "uart0";
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interrupt-parent = <&intc>;
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interrupts = <20>;
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reg-shift = <2>;
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};
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uart1: uart1@d00 {
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compatible = "ns16550a";
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reg = <0xd00 0x100>;
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clock-frequency = <40000000>;
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resets = <&resetc 19>;
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reset-names = "uart1";
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interrupt-parent = <&intc>;
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interrupts = <21>;
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reg-shift = <2>;
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};
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uart2: uart2@e00 {
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compatible = "ns16550a";
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reg = <0xe00 0x100>;
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clock-frequency = <40000000>;
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resets = <&resetc 20>;
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reset-names = "uart2";
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interrupt-parent = <&intc>;
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interrupts = <22>;
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reg-shift = <2>;
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};
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};
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eth@10110000 {
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compatible = "mediatek,mt7628-eth";
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reg = <0x10100000 0x10000
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0x10110000 0x8000>;
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syscon = <&sysc>;
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};
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usb_phy: usb-phy@10120000 {
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compatible = "mediatek,mt7628-usbphy";
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reg = <0x10120000 0x1000>;
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#phy-cells = <0>;
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ralink,sysctl = <&sysc>;
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resets = <&resetc 22 &resetc 25>;
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reset-names = "host", "device";
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};
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ehci@101c0000 {
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compatible = "generic-ehci";
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reg = <0x101c0000 0x1000>;
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phys = <&usb_phy>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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};
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