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d1c3b27525
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
195 lines
5.2 KiB
C
195 lines
5.2 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc405.h>
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/* test-only: move into cpu directory!!! */
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#if defined(PLLMR0_200_133_66)
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void board_pll_init_f(void)
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{
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/*
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* set PLL clocks based on input sysclk is 33M
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*
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* ----------------------------------
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* | CLK | FREQ (MHz) | DIV RATIO |
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* ----------------------------------
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* | CPU | 200.0 | 4 (0x02)|
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* | PLB | 133.3 | 6 (0x06)|
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* | OPB | 66.6 | 12 (0x0C)|
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* | EBC | 66.6 | 12 (0x0C)|
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* | SPI | 66.6 | 12 (0x0C)|
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* | UART0 | 10.0 | 40 (0x28)|
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* | UART1 | 10.0 | 40 (0x28)|
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* | DAC | 2.0 | 200 (0xC8)|
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* | ADC | 2.0 | 200 (0xC8)|
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* | PWM | 100.0 | 4 (0x04)|
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* | EMAC | 25.0 | 16 (0x10)|
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* -----------------------------------
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*/
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/* Initialize PLL */
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mtcpr(CPR0_PLLC, 0x0000033c);
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mtcpr(CPR0_PLLD, 0x0c010200);
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mtcpr(CPC0_PRIMAD, 0x04060c0c);
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mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
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mtcpr(CPR0_CLKUP, 0x40000000);
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}
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#elif defined(PLLMR0_266_160_80)
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void board_pll_init_f(void)
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{
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/*
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* set PLL clocks based on input sysclk is 33M
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*
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* ----------------------------------
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* | CLK | FREQ (MHz) | DIV RATIO |
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* ----------------------------------
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* | CPU | 266.64 | 3 |
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* | PLB | 159.98 | 5 (0x05)|
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* | OPB | 79.99 | 10 (0x0A)|
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* | EBC | 79.99 | 10 (0x0A)|
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* | SPI | 79.99 | 10 (0x0A)|
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* | UART0 | 28.57 | 7 (0x07)|
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* | UART1 | 28.57 | 7 (0x07)|
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* | DAC | 28.57 | 7 (0xA7)|
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* | ADC | 4 | 50 (0x32)|
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* | PWM | 28.57 | 7 (0x07)|
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* | EMAC | 4 | 50 (0x32)|
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* -----------------------------------
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*/
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/* Initialize PLL */
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mtcpr(CPR0_PLLC, 0x20000238);
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mtcpr(CPR0_PLLD, 0x03010400);
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mtcpr(CPC0_PRIMAD, 0x03050a0a);
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mtcpr(CPC0_PERC0, 0x00000000);
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mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
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mtcpr(CPC0_PERD1, 0x07323200);
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mtcpr(CPR0_CLKUP, 0x40000000);
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}
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#elif defined(PLLMR0_333_166_83)
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void board_pll_init_f(void)
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{
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/*
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* set PLL clocks based on input sysclk is 33M
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*
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* ----------------------------------
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* | CLK | FREQ (MHz) | DIV RATIO |
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* ----------------------------------
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* | CPU | 333.33 | 2 |
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* | PLB | 166.66 | 4 (0x04)|
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* | OPB | 83.33 | 8 (0x08)|
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* | EBC | 83.33 | 8 (0x08)|
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* | SPI | 83.33 | 8 (0x08)|
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* | UART0 | 16.66 | 5 (0x05)|
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* | UART1 | 16.66 | 5 (0x05)|
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* | DAC | ???? | 166 (0xA6)|
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* | ADC | ???? | 166 (0xA6)|
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* | PWM | 41.66 | 3 (0x03)|
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* | EMAC | ???? | 3 (0x03)|
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* -----------------------------------
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*/
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/* Initialize PLL */
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mtcpr(CPR0_PLLC, 0x0000033C);
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mtcpr(CPR0_PLLD, 0x0a010000);
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mtcpr(CPC0_PRIMAD, 0x02040808);
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mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
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mtcpr(CPC0_PERD1, 0xA6A60300);
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mtcpr(CPR0_CLKUP, 0x40000000);
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}
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#elif defined(PLLMR0_100_100_12)
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void board_pll_init_f(void)
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{
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/*
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* set PLL clocks based on input sysclk is 33M
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*
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* ----------------------
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* | CLK | FREQ (MHz) |
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* ----------------------
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* | CPU | 100.00 |
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* | PLB | 100.00 |
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* | OPB | 12.00 |
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* | EBC | 49.00 |
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* ----------------------
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*/
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/* Initialize PLL */
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mtcpr(CPR0_PLLC, 0x000003BC);
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mtcpr(CPR0_PLLD, 0x06060600);
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mtcpr(CPC0_PRIMAD, 0x02020004);
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mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
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mtcpr(CPC0_PERD1, 0xC8C81600);
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mtcpr(CPR0_CLKUP, 0x40000000);
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}
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#endif /* CPU_<speed>_405EZ */
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#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk(void)
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{
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unsigned long cpr_plld;
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unsigned long cpr_primad;
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unsigned long primad_cpudv;
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unsigned long pllFbkDiv;
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unsigned long freqProcessor;
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/*
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* Read PLL Mode registers
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*/
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mfcpr(CPR0_PLLD, cpr_plld);
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/*
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* Read CPR_PRIMAD register
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*/
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mfcpr(CPC0_PRIMAD, cpr_primad);
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/*
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* Determine CPU clock frequency
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*/
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primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
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if (primad_cpudv == 0)
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primad_cpudv = 16;
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/*
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* Determine FBK_DIV.
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*/
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pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
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if (pllFbkDiv == 0)
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pllFbkDiv = 256;
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freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
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return (freqProcessor);
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}
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#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
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