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3d31538625
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/*
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* keystone2: common pll clock definitions
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCK_DEFS_H_
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#define _CLOCK_DEFS_H_
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#include <asm/arch/hardware.h>
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#define BIT(x) (1 << (x))
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/* PLL Control Registers */
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struct pllctl_regs {
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u32 ctl; /* 00 */
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u32 ocsel; /* 04 */
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u32 secctl; /* 08 */
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u32 resv0;
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u32 mult; /* 10 */
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u32 prediv; /* 14 */
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u32 div1; /* 18 */
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u32 div2; /* 1c */
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u32 div3; /* 20 */
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u32 oscdiv1; /* 24 */
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u32 resv1; /* 28 */
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u32 bpdiv; /* 2c */
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u32 wakeup; /* 30 */
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u32 resv2;
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u32 cmd; /* 38 */
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u32 stat; /* 3c */
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u32 alnctl; /* 40 */
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u32 dchange; /* 44 */
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u32 cken; /* 48 */
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u32 ckstat; /* 4c */
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u32 systat; /* 50 */
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u32 ckctl; /* 54 */
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u32 resv3[2];
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u32 div4; /* 60 */
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u32 div5; /* 64 */
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u32 div6; /* 68 */
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u32 div7; /* 6c */
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u32 div8; /* 70 */
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u32 div9; /* 74 */
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u32 div10; /* 78 */
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u32 div11; /* 7c */
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u32 div12; /* 80 */
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};
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static struct pllctl_regs *pllctl_regs[] = {
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(struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
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};
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#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
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#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
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#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
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#define pllctl_reg_rmw(pll, reg, mask, val) \
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pllctl_reg_write(pll, reg, \
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(pllctl_reg_read(pll, reg) & ~(mask)) | val)
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#define pllctl_reg_setbits(pll, reg, mask) \
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pllctl_reg_rmw(pll, reg, 0, mask)
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#define pllctl_reg_clrbits(pll, reg, mask) \
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pllctl_reg_rmw(pll, reg, mask, 0)
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#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
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/* PLLCTL Bits */
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#define PLLCTL_BYPASS BIT(23)
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#define PLL_PLLRST BIT(14)
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#define PLLCTL_PAPLL BIT(13)
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#define PLLCTL_CLKMODE BIT(8)
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#define PLLCTL_PLLSELB BIT(7)
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#define PLLCTL_ENSAT BIT(6)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLEN BIT(0)
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#define PLLSTAT_GO BIT(0)
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#define MAIN_ENSAT_OFFSET 6
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#define PLLDIV_ENABLE BIT(15)
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#define PLL_DIV_MASK 0x3f
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#define PLL_MULT_MASK 0x1fff
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#define PLL_MULT_SHIFT 6
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#define PLLM_MULT_HI_MASK 0x7f
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#define PLLM_MULT_HI_SHIFT 12
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#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
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#define PLLM_MULT_LO_MASK 0x3f
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#define PLL_CLKOD_MASK 0xf
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#define PLL_CLKOD_SHIFT 19
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#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
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#define PLL_BWADJ_LO_MASK 0xff
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#define PLL_BWADJ_LO_SHIFT 24
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#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
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#define PLL_BWADJ_HI_MASK 0xf
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#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
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#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
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#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
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#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
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#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
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#endif /* _CLOCK_DEFS_H_ */
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