mirror of
https://github.com/AsahiLinux/u-boot
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d1998a9fde
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
667 lines
15 KiB
C
667 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2019 NXP
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*
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* PCIe DM U-Boot driver for Freescale PowerPC SoCs
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* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "pcie_fsl.h"
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#include <dm/device_compat.h>
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LIST_HEAD(fsl_pcie_list);
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static int fsl_pcie_link_up(struct fsl_pcie *pcie);
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static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
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{
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struct udevice *bus = pcie->bus;
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if (!pcie->enabled)
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return -ENXIO;
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if (PCI_BUS(bdf) < bus->seq)
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return -EINVAL;
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if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
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return -EINVAL;
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if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
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return -EINVAL;
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if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
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return -EINVAL;
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return 0;
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}
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static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct fsl_pcie *pcie = dev_get_priv(bus);
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ccsr_fsl_pci_t *regs = pcie->regs;
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u32 val;
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if (fsl_pcie_addr_valid(pcie, bdf)) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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bdf = bdf - PCI_BDF(bus->seq, 0, 0);
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val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
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out_be32(®s->cfg_addr, val);
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sync();
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switch (size) {
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case PCI_SIZE_8:
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*valuep = in_8((u8 *)®s->cfg_data + (offset & 3));
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break;
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case PCI_SIZE_16:
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*valuep = in_le16((u16 *)((u8 *)®s->cfg_data +
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(offset & 2)));
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break;
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case PCI_SIZE_32:
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*valuep = in_le32(®s->cfg_data);
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break;
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}
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return 0;
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}
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static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct fsl_pcie *pcie = dev_get_priv(bus);
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ccsr_fsl_pci_t *regs = pcie->regs;
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u32 val;
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u8 val_8;
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u16 val_16;
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u32 val_32;
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if (fsl_pcie_addr_valid(pcie, bdf))
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return 0;
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bdf = bdf - PCI_BDF(bus->seq, 0, 0);
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val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
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out_be32(®s->cfg_addr, val);
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sync();
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switch (size) {
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case PCI_SIZE_8:
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val_8 = value;
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out_8((u8 *)®s->cfg_data + (offset & 3), val_8);
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break;
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case PCI_SIZE_16:
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val_16 = value;
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out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16);
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break;
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case PCI_SIZE_32:
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val_32 = value;
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out_le32(®s->cfg_data, val_32);
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break;
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}
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return 0;
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}
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static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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int ret;
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struct udevice *bus = pcie->bus;
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ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
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offset, valuep, size);
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return ret;
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}
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static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
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ulong value, enum pci_size_t size)
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{
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struct udevice *bus = pcie->bus;
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return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
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offset, value, size);
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}
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static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
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u8 *valuep)
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{
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ulong val;
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int ret;
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ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
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*valuep = val;
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return ret;
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}
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static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
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u16 *valuep)
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{
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ulong val;
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int ret;
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ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
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*valuep = val;
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return ret;
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}
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static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
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u32 *valuep)
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{
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ulong val;
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int ret;
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ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
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*valuep = val;
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return ret;
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}
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static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
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u8 value)
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{
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return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
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}
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static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
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u16 value)
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{
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return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
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}
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static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
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u32 value)
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{
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return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
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}
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static int fsl_pcie_link_up(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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u16 ltssm;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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ltssm = (in_be32(®s->pex_csr0)
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& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
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return ltssm == LTSSM_L0_REV3;
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}
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fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
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return ltssm == LTSSM_L0;
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}
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static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
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{
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u8 header_type;
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fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
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return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
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}
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static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
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{
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struct pci_region *io, *mem, *pref;
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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if (mem)
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set_next_law(mem->phys_start,
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law_size_bits(mem->size),
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pcie->law_trgt_if);
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if (io)
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set_next_law(io->phys_start,
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law_size_bits(io->size),
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pcie->law_trgt_if);
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return 0;
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}
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static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY);
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return;
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}
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fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
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}
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static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
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int type, u64 phys, u64 bus_addr,
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pci_size_t size)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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pot_t *po = ®s->pot[idx];
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u32 war, sz;
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if (idx < 0)
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return -EINVAL;
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out_be32(&po->powbar, phys >> 12);
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out_be32(&po->potar, bus_addr >> 12);
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#ifdef CONFIG_SYS_PCI_64BIT
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out_be32(&po->potear, bus_addr >> 44);
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#else
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out_be32(&po->potear, 0);
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#endif
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sz = (__ilog2_u64((u64)size) - 1);
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war = POWAR_EN | sz;
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if (type == PCI_REGION_IO)
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war |= POWAR_IO_READ | POWAR_IO_WRITE;
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else
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war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
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out_be32(&po->powar, war);
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return 0;
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}
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static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
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bool pf, u64 phys, u64 bus_addr,
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pci_size_t size)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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pit_t *pi = ®s->pit[idx];
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u32 sz = (__ilog2_u64(size) - 1);
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u32 flag = PIWAR_LOCAL;
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if (idx < 0)
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return -EINVAL;
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out_be32(&pi->pitar, phys >> 12);
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out_be32(&pi->piwbar, bus_addr >> 12);
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#ifdef CONFIG_SYS_PCI_64BIT
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out_be32(&pi->piwbear, bus_addr >> 44);
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#else
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out_be32(&pi->piwbear, 0);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
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flag = 0;
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#endif
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flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
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if (pf)
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flag |= PIWAR_PF;
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out_be32(&pi->piwar, flag | sz);
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return 0;
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}
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static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
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{
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struct pci_region *io, *mem, *pref;
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int idx = 1; /* skip 0 */
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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if (io)
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/* ATU : OUTBOUND : IO */
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fsl_pcie_setup_outbound_win(pcie, idx++,
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PCI_REGION_IO,
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io->phys_start,
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io->bus_start,
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io->size);
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if (mem)
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/* ATU : OUTBOUND : MEM */
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fsl_pcie_setup_outbound_win(pcie, idx++,
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PCI_REGION_MEM,
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mem->phys_start,
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mem->bus_start,
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mem->size);
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return 0;
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}
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static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
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{
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phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
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pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
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u64 sz = min((u64)gd->ram_size, (1ull << 32));
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pci_size_t pci_sz;
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int idx;
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if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
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idx = 2;
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else
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idx = 3;
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pci_sz = 1ull << __ilog2_u64(sz);
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dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)bus_start, (u64)phys_start, (u64)sz);
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/* if we aren't an exact power of two match, pci_sz is smaller
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* round it up to the next power of two. We report the actual
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* size to pci region tracking.
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*/
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if (pci_sz != sz)
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sz = 2ull << __ilog2_u64(sz);
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fsl_pcie_setup_inbound_win(pcie, idx--, true,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_BUS, sz);
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#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
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/*
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* On 64-bit capable systems, set up a mapping for all of DRAM
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* in high pci address space.
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*/
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pci_sz = 1ull << __ilog2_u64(gd->ram_size);
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/* round up to the next largest power of two */
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if (gd->ram_size > pci_sz)
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pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
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dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
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(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
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fsl_pcie_setup_inbound_win(pcie, idx--, true,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
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#endif
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return 0;
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}
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static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
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{
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fsl_pcie_setup_outbound_wins(pcie);
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fsl_pcie_setup_inbound_wins(pcie);
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return 0;
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}
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static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie,
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bool enable)
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{
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u32 val;
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fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val);
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if (enable)
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val |= 1;
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else
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val &= ~1;
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fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val);
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}
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static int fsl_pcie_init_port(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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u32 val_32;
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u16 val_16;
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fsl_pcie_init_atmu(pcie);
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#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
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val_32 = 0;
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fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
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val_32 &= ~0x03;
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fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
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udelay(1);
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#endif
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#ifdef CONFIG_FSL_PCIE_RESET
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u16 ltssm;
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int i;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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/* assert PCIe reset */
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setbits_be32(®s->pdb_stat, 0x08000000);
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(void)in_be32(®s->pdb_stat);
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udelay(1000);
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/* clear PCIe reset */
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clrbits_be32(®s->pdb_stat, 0x08000000);
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asm("sync;isync");
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for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
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udelay(1000);
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} else {
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fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
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if (ltssm == 1) {
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/* assert PCIe reset */
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setbits_be32(®s->pdb_stat, 0x08000000);
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(void)in_be32(®s->pdb_stat);
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udelay(100);
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/* clear PCIe reset */
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clrbits_be32(®s->pdb_stat, 0x08000000);
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asm("sync;isync");
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for (i = 0; i < 100 &&
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!fsl_pcie_link_up(pcie); i++)
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udelay(1000);
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}
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}
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
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if (!fsl_pcie_link_up(pcie)) {
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serdes_corenet_t *srds_regs;
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srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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val_32 = in_be32(&srds_regs->srdspccr0);
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if ((val_32 >> 28) == 3) {
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int i;
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out_be32(&srds_regs->srdspccr0, 2 << 28);
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setbits_be32(®s->pdb_stat, 0x08000000);
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in_be32(®s->pdb_stat);
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udelay(100);
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clrbits_be32(®s->pdb_stat, 0x08000000);
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asm("sync;isync");
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for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
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udelay(1000);
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}
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}
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#endif
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/*
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* The Read-Only Write Enable bit defaults to 1 instead of 0.
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* Set to 0 to protect the read-only registers.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
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fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
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#endif
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/*
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* Enable All Error Interrupts except
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* - Master abort (pci)
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* - Master PERR (pci)
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* - ICCA (PCIe)
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*/
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out_be32(®s->peer, ~0x20140);
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/* set URR, FER, NFER (but not CER) */
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fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
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val_32 |= 0xf000e;
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fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
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/* Clear all error indications */
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out_be32(®s->pme_msg_det, 0xffffffff);
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out_be32(®s->pme_msg_int_en, 0xffffffff);
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out_be32(®s->pedr, 0xffffffff);
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fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
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if (val_16)
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fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
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fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
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if (val_16)
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fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
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return 0;
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}
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static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
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{
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u32 classcode_reg;
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u32 val;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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classcode_reg = PCI_CLASS_REVISION;
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fsl_pcie_dbi_read_only_reg_write_enable(pcie, true);
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} else {
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classcode_reg = CSR_CLASSCODE;
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}
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fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
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val &= 0xff;
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val |= PCI_CLASS_BRIDGE_PCI << 16;
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fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
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fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
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return 0;
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}
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static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
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{
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return fsl_pcie_fixup_classcode(pcie);
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}
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static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
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{
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fsl_pcie_config_ready(pcie);
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return 0;
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}
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static int fsl_pcie_probe(struct udevice *dev)
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{
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struct fsl_pcie *pcie = dev_get_priv(dev);
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ccsr_fsl_pci_t *regs = pcie->regs;
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u16 val_16;
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pcie->bus = dev;
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pcie->block_rev = in_be32(®s->block_rev1);
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list_add(&pcie->list, &fsl_pcie_list);
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pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
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if (!pcie->enabled) {
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printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
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return 0;
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}
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fsl_pcie_setup_law(pcie);
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pcie->mode = fsl_pcie_is_agent(pcie);
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fsl_pcie_init_port(pcie);
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printf("PCIe%d: %s ", pcie->idx, dev->name);
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if (pcie->mode) {
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printf("Endpoint");
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fsl_pcie_init_ep(pcie);
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} else {
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printf("Root Complex");
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fsl_pcie_init_rc(pcie);
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}
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if (!fsl_pcie_link_up(pcie)) {
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printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
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return 0;
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}
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fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
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printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
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return 0;
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}
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static int fsl_pcie_of_to_plat(struct udevice *dev)
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{
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struct fsl_pcie *pcie = dev_get_priv(dev);
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struct fsl_pcie_data *info;
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int ret;
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pcie->regs = dev_remap_addr(dev);
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if (!pcie->regs) {
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pr_err("\"reg\" resource not found\n");
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return -EINVAL;
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}
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ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
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if (ret < 0) {
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pr_err("\"law_trgt_if\" not found\n");
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return ret;
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}
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info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
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pcie->info = info;
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pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
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info->block_offset) / info->stride;
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return 0;
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}
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static const struct dm_pci_ops fsl_pcie_ops = {
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.read_config = fsl_pcie_read_config,
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.write_config = fsl_pcie_write_config,
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};
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static struct fsl_pcie_data p1_p2_data = {
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.block_offset = 0xa000,
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.block_offset_mask = 0xffff,
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.stride = 0x1000,
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};
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static struct fsl_pcie_data p2041_data = {
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.block_offset = 0x200000,
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.block_offset_mask = 0x3fffff,
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.stride = 0x1000,
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};
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static struct fsl_pcie_data t2080_data = {
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.block_offset = 0x240000,
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.block_offset_mask = 0x3fffff,
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.stride = 0x10000,
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};
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static const struct udevice_id fsl_pcie_ids[] = {
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{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
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{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
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{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
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{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
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{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
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{ .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
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{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
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{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
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{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
|
|
{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
|
|
{ }
|
|
};
|
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|
|
U_BOOT_DRIVER(fsl_pcie) = {
|
|
.name = "fsl_pcie",
|
|
.id = UCLASS_PCI,
|
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.of_match = fsl_pcie_ids,
|
|
.ops = &fsl_pcie_ops,
|
|
.of_to_plat = fsl_pcie_of_to_plat,
|
|
.probe = fsl_pcie_probe,
|
|
.priv_auto = sizeof(struct fsl_pcie),
|
|
};
|