mirror of
https://github.com/AsahiLinux/u-boot
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61290fb52c
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2:
- coding style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
Changes for v5:
- coding style cleanup
81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ddr.h>
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#include <mach/ath79.h>
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#include <debug_uart.h>
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#define RST_RESET_RTC_RESET_LSB 27
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#define RST_RESET_RTC_RESET_MASK 0x08000000
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#define RST_RESET_RTC_RESET_SET(x) \
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(((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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void __iomem *regs;
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u32 val;
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regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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MAP_NOCACHE);
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/* UART : RX18, TX22 done
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* GPIO18 as input, GPIO22 as output
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*/
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val = readl(regs + AR71XX_GPIO_REG_OE);
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val |= QCA956X_GPIO(18);
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val &= ~QCA956X_GPIO(22);
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writel(val, regs + AR71XX_GPIO_REG_OE);
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/*
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* Enable GPIO22 as UART0_SOUT
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*/
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val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5);
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val &= ~QCA956X_GPIO_MUX_MASK(16);
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val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16;
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writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5);
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/*
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* Enable GPIO18 as UART0_SIN
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*/
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val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0);
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val &= ~QCA956X_GPIO_MUX_MASK(8);
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val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8;
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writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0);
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/*
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* Enable GPIO22 output
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*/
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val = readl(regs + AR71XX_GPIO_REG_OUT);
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val |= QCA956X_GPIO(22);
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writel(val, regs + AR71XX_GPIO_REG_OUT);
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}
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#endif
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int board_early_init_f(void)
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{
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u32 reg;
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void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
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AR71XX_RESET_SIZE, MAP_NOCACHE);
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* CPU:775, DDR:650, AHB:258 */
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qca956x_pll_init();
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qca956x_ddr_init();
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#endif
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/* Take WMAC out of reset */
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reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE);
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reg &= (~RST_RESET_RTC_RESET_SET(1));
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writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE);
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ath79_eth_reset();
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return 0;
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}
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