Eric Nelson 7f17fb7400 mx6: ddr: pass mx6_ddr_sysinfo to calibration routines ... The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>		2016-11-29 16:40:12 +01:00
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Kconfig	mx6: remove SYS_SOC from board Kconfig	2015-09-13 10:37:29 +02:00
MAINTAINERS	novena: Add MAINTAINERS file	2014-11-03 11:30:50 +01:00
Makefile	arm: mx6: novena: Pull video handling into separate file	2014-12-30 14:06:43 +01:00
novena.c	treewide: replace #include <asm/errno.h> with <linux/errno.h>	2016-09-23 17:55:42 -04:00
novena.h	arm: mx6: novena: Add proper LVDS display support	2014-12-30 14:10:31 +01:00
novena_spl.c	mx6: ddr: pass mx6_ddr_sysinfo to calibration routines	2016-11-29 16:40:12 +01:00
video.c	treewide: replace #include <asm/errno.h> with <linux/errno.h>	2016-09-23 17:55:42 -04:00