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79887749f8
This patch adds a phy driver for the Micrel KSZ886x switches. Similarly to the KSZ8895, SoC MAC is directly connected to the switch MAC on the switch CPU port, so the link to the switch is always up. KSZ886x switches can be used in the following configuration modes: - Unmanaged mode with config stored in external EEPROM - Managed mode over SPI - Managed mode over I2C - Managed mode over mdio/mdc (aka MIIM or SMI) This patch supports only unmanaged and MIIM modes. Based on Micrel KSZ886x driver from Linux kernel and Micrel KSZ8895 driver from U-Boot. Verified with the KSZ8863MLL. Signed-off-by: Alexey Firago <alexey_firago@mentor.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
530 lines
13 KiB
C
530 lines
13 KiB
C
/*
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* Micrel PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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* (C) 2012 NetModule AG, David Andrey, added KSZ9031
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <micrel.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct phy_driver KSZ804_driver = {
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.name = "Micrel KSZ804",
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.uid = 0x221510,
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.mask = 0xfffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &genphy_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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#define MII_KSZPHY_OMSO 0x16
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#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
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static int ksz_genconfig_bcastoff(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
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if (ret < 0)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
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ret | KSZPHY_OMSO_B_CAST_OFF);
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if (ret < 0)
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return ret;
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return genphy_config(phydev);
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}
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static struct phy_driver KSZ8031_driver = {
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.name = "Micrel KSZ8021/KSZ8031",
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.uid = 0x221550,
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.mask = 0xfffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &ksz_genconfig_bcastoff,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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/**
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* KSZ8051
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*/
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#define MII_KSZ8051_PHY_OMSO 0x16
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#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5)
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static int ksz8051_config(struct phy_device *phydev)
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{
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unsigned val;
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/* Disable NAND-tree */
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val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
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val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
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return genphy_config(phydev);
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}
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static struct phy_driver KSZ8051_driver = {
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.name = "Micrel KSZ8051",
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.uid = 0x221550,
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.mask = 0xfffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &ksz8051_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver KSZ8081_driver = {
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.name = "Micrel KSZ8081",
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.uid = 0x221560,
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.mask = 0xfffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &ksz_genconfig_bcastoff,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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/**
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* KSZ8895
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*/
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static unsigned short smireg_to_phy(unsigned short reg)
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{
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return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
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}
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static unsigned short smireg_to_reg(unsigned short reg)
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{
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return reg & 0x1F;
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}
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static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
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{
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phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
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smireg_to_reg(smireg), val);
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}
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#if 0
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static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
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{
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return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
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MDIO_DEVAD_NONE, smireg_to_reg(smireg));
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}
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#endif
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int ksz8895_config(struct phy_device *phydev)
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{
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/* we are connected directly to the switch without
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* dedicated PHY. SCONF1 == 001 */
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phydev->link = 1;
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_100;
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/* Force the switch to start */
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ksz8895_write_smireg(phydev, 1, 1);
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return 0;
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}
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static int ksz8895_startup(struct phy_device *phydev)
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{
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return 0;
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}
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static struct phy_driver ksz8895_driver = {
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.name = "Micrel KSZ8895/KSZ8864",
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.uid = 0x221450,
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.mask = 0xffffe1,
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.features = PHY_BASIC_FEATURES,
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.config = &ksz8895_config,
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.startup = &ksz8895_startup,
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.shutdown = &genphy_shutdown,
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};
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#ifndef CONFIG_PHY_MICREL_KSZ9021
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/*
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* I can't believe Micrel used the exact same part number
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* for the KSZ9021. Shame Micrel, Shame!
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*/
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static struct phy_driver KS8721_driver = {
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.name = "Micrel KS8721BL",
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.uid = 0x221610,
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.mask = 0xfffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &genphy_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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#endif
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/*
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* KSZ9021 - KSZ9031 common
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*/
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#define MII_KSZ90xx_PHY_CTL 0x1f
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#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
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#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
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#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
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#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
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static int ksz90xx_startup(struct phy_device *phydev)
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{
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unsigned phy_ctl;
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
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if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
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phydev->speed = SPEED_1000;
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else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
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phydev->speed = SPEED_100;
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else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
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phydev->speed = SPEED_10;
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return 0;
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}
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/* Common OF config bits for KSZ9021 and KSZ9031 */
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#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
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#ifdef CONFIG_DM_ETH
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struct ksz90x1_reg_field {
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const char *name;
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const u8 size; /* Size of the bitfield, in bits */
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const u8 off; /* Offset from bit 0 */
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const u8 dflt; /* Default value */
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};
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struct ksz90x1_ofcfg {
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const u16 reg;
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const u16 devad;
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const struct ksz90x1_reg_field *grp;
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const u16 grpsz;
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};
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static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
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{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
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{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
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};
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static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
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{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
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{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
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};
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static int ksz90x1_of_config_group(struct phy_device *phydev,
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struct ksz90x1_ofcfg *ofcfg)
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{
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struct udevice *dev = phydev->dev;
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struct phy_driver *drv = phydev->drv;
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const int ps_to_regval = 60;
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int val[4];
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int i, changed = 0, offset, max;
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u16 regval = 0;
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if (!drv || !drv->writeext)
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return -EOPNOTSUPP;
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for (i = 0; i < ofcfg->grpsz; i++) {
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val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
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ofcfg->grp[i].name, -1);
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offset = ofcfg->grp[i].off;
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if (val[i] == -1) {
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/* Default register value for KSZ9021 */
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regval |= ofcfg->grp[i].dflt << offset;
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} else {
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changed = 1; /* Value was changed in OF */
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/* Calculate the register value and fix corner cases */
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if (val[i] > ps_to_regval * 0xf) {
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max = (1 << ofcfg->grp[i].size) - 1;
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regval |= max << offset;
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} else {
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regval |= (val[i] / ps_to_regval) << offset;
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}
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}
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}
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if (!changed)
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return 0;
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return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
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}
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#endif
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#endif
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#ifdef CONFIG_PHY_MICREL_KSZ9021
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/*
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* KSZ9021
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*/
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/* PHY Registers */
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#define MII_KSZ9021_EXTENDED_CTRL 0x0b
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#define MII_KSZ9021_EXTENDED_DATAW 0x0c
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#define MII_KSZ9021_EXTENDED_DATAR 0x0d
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#define CTRL1000_PREFER_MASTER (1 << 10)
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#define CTRL1000_CONFIG_MASTER (1 << 11)
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#define CTRL1000_MANUAL_CONFIG (1 << 12)
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#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
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defined(CONFIG_PHY_MICREL_KSZ9031))
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static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
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{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
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{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
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};
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static int ksz9021_of_config(struct phy_device *phydev)
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{
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struct ksz90x1_ofcfg ofcfg[] = {
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{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
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{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
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{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
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};
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
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ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
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if (ret)
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return ret;
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return 0;
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}
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#else
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static int ksz9021_of_config(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
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{
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/* extended registers */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
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return phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9021_EXTENDED_DATAW, val);
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}
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int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
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{
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/* extended registers */
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phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
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return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
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}
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static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
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int regnum)
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{
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return ksz9021_phy_extended_read(phydev, regnum);
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}
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static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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return ksz9021_phy_extended_write(phydev, regnum, val);
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}
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/* Micrel ksz9021 */
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static int ksz9021_config(struct phy_device *phydev)
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{
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unsigned ctrl1000 = 0;
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const unsigned master = CTRL1000_PREFER_MASTER |
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CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
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unsigned features = phydev->drv->features;
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int ret;
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ret = ksz9021_of_config(phydev);
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if (ret)
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return ret;
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if (getenv("disable_giga"))
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features &= ~(SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full);
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/* force master mode for 1000BaseT due to chip errata */
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if (features & SUPPORTED_1000baseT_Half)
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ctrl1000 |= ADVERTISE_1000HALF | master;
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if (features & SUPPORTED_1000baseT_Full)
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ctrl1000 |= ADVERTISE_1000FULL | master;
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phydev->advertising = phydev->supported = features;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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return 0;
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}
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static struct phy_driver ksz9021_driver = {
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.name = "Micrel ksz9021",
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.uid = 0x221610,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &ksz9021_config,
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.startup = &ksz90xx_startup,
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.shutdown = &genphy_shutdown,
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.writeext = &ksz9021_phy_extwrite,
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.readext = &ksz9021_phy_extread,
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};
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#endif
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/**
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* KSZ9031
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*/
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/* PHY Registers */
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#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
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#define MII_KSZ9031_MMD_REG_DATA 0x0e
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#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
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defined(CONFIG_PHY_MICREL_KSZ9031))
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static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
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{ { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
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static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
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{ { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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struct ksz90x1_ofcfg ofcfg[] = {
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{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
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{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
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{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
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{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
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};
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
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ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
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if (ret)
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return ret;
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return 0;
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}
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#else
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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/* Accessors to extended registers*/
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int ksz9031_phy_extended_write(struct phy_device *phydev,
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int devaddr, int regnum, u16 mode, u16 val)
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{
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/*select register addr for mmd*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
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/*select register for mmd*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, regnum);
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/*setup mode*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
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/*write the value*/
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return phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, val);
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}
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int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
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int regnum, u16 mode)
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{
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, regnum);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
|
|
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
|
|
}
|
|
|
|
static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
|
|
int regnum)
|
|
{
|
|
return ksz9031_phy_extended_read(phydev, devaddr, regnum,
|
|
MII_KSZ9031_MOD_DATA_NO_POST_INC);
|
|
};
|
|
|
|
static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
|
|
int devaddr, int regnum, u16 val)
|
|
{
|
|
return ksz9031_phy_extended_write(phydev, devaddr, regnum,
|
|
MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
|
|
};
|
|
|
|
static int ksz9031_config(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
ret = ksz9031_of_config(phydev);
|
|
if (ret)
|
|
return ret;
|
|
return genphy_config(phydev);
|
|
}
|
|
|
|
static struct phy_driver ksz9031_driver = {
|
|
.name = "Micrel ksz9031",
|
|
.uid = 0x221620,
|
|
.mask = 0xfffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &ksz9031_config,
|
|
.startup = &ksz90xx_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
.writeext = &ksz9031_phy_extwrite,
|
|
.readext = &ksz9031_phy_extread,
|
|
};
|
|
|
|
int ksz886x_config(struct phy_device *phydev)
|
|
{
|
|
/* we are connected directly to the switch without
|
|
* dedicated PHY. */
|
|
phydev->link = 1;
|
|
phydev->duplex = DUPLEX_FULL;
|
|
phydev->speed = SPEED_100;
|
|
return 0;
|
|
}
|
|
|
|
static int ksz886x_startup(struct phy_device *phydev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver ksz886x_driver = {
|
|
.name = "Micrel KSZ886x Switch",
|
|
.uid = 0x00221430,
|
|
.mask = 0xfffff0,
|
|
.features = PHY_BASIC_FEATURES,
|
|
.config = &ksz886x_config,
|
|
.startup = &ksz886x_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
int phy_micrel_init(void)
|
|
{
|
|
phy_register(&KSZ804_driver);
|
|
phy_register(&KSZ8031_driver);
|
|
phy_register(&KSZ8051_driver);
|
|
phy_register(&KSZ8081_driver);
|
|
#ifdef CONFIG_PHY_MICREL_KSZ9021
|
|
phy_register(&ksz9021_driver);
|
|
#else
|
|
phy_register(&KS8721_driver);
|
|
#endif
|
|
phy_register(&ksz9031_driver);
|
|
phy_register(&ksz8895_driver);
|
|
phy_register(&ksz886x_driver);
|
|
return 0;
|
|
}
|