mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
409 lines
10 KiB
Text
409 lines
10 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* DTS File for HiSilicon Hi3798cv200 SoC.
|
|
*
|
|
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
|
|
*/
|
|
|
|
#include <dt-bindings/clock/histb-clock.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/reset/ti-syscon.h>
|
|
|
|
/ {
|
|
compatible = "hisilicon,hi3798cv200";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@2 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@f1001000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
|
|
<0x0 0xf1002000 0x0 0x100>; /* GICC */
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
soc: soc@f0000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0xf0000000 0x10000000>;
|
|
|
|
crg: clock-reset-controller@8a22000 {
|
|
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
|
|
reg = <0x8a22000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <2>;
|
|
|
|
gmacphyrst: reset-controller {
|
|
compatible = "ti,syscon-reset";
|
|
#reset-cells = <1>;
|
|
ti,reset-bits =
|
|
<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
|
|
DEASSERT_SET|STATUS_NONE)>,
|
|
<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
|
|
DEASSERT_SET|STATUS_NONE)>;
|
|
};
|
|
};
|
|
|
|
sysctrl: system-controller@8000000 {
|
|
compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
|
|
reg = <0x8000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <2>;
|
|
};
|
|
|
|
uart0: serial@8b00000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x8b00000 0x1000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&sysctrl HISTB_UART0_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@8b02000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x8b02000 0x1000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&crg HISTB_UART2_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@8b10000 {
|
|
compatible = "hisilicon,hix5hd2-i2c";
|
|
reg = <0x8b10000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
clocks = <&crg HISTB_I2C0_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@8b11000 {
|
|
compatible = "hisilicon,hix5hd2-i2c";
|
|
reg = <0x8b11000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
clocks = <&crg HISTB_I2C1_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@8b12000 {
|
|
compatible = "hisilicon,hix5hd2-i2c";
|
|
reg = <0x8b12000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
clocks = <&crg HISTB_I2C2_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@8b13000 {
|
|
compatible = "hisilicon,hix5hd2-i2c";
|
|
reg = <0x8b13000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
clocks = <&crg HISTB_I2C3_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@8b14000 {
|
|
compatible = "hisilicon,hix5hd2-i2c";
|
|
reg = <0x8b14000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
clocks = <&crg HISTB_I2C4_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@8b1a000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x8b1a000 0x1000>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
num-cs = <1>;
|
|
cs-gpios = <&gpio7 1 0>;
|
|
clocks = <&crg HISTB_SPI0_CLK>;
|
|
clock-names = "apb_pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: mmc@9830000 {
|
|
compatible = "snps,dw-mshc";
|
|
reg = <0x9830000 0x10000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&crg HISTB_MMC_CIU_CLK>,
|
|
<&crg HISTB_MMC_BIU_CLK>;
|
|
clock-names = "ciu", "biu";
|
|
};
|
|
|
|
gpio0: gpio@8b20000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b20000 0x1000>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio1: gpio@8b21000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b21000 0x1000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio2: gpio@8b22000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b22000 0x1000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio3: gpio@8b23000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b23000 0x1000>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio4: gpio@8b24000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b24000 0x1000>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio5: gpio@8004000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8004000 0x1000>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio6: gpio@8b26000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b26000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio7: gpio@8b27000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b27000 0x1000>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio8: gpio@8b28000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b28000 0x1000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio9: gpio@8b29000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b29000 0x1000>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio10: gpio@8b2a000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b2a000 0x1000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio11: gpio@8b2b000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b2b000 0x1000>;
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio12: gpio@8b2c000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x8b2c000 0x1000>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&crg HISTB_APB_CLK>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac0: ethernet@9840000 {
|
|
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
|
|
reg = <0x9840000 0x1000>,
|
|
<0x984300c 0x4>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&crg HISTB_ETH0_MAC_CLK>,
|
|
<&crg HISTB_ETH0_MACIF_CLK>;
|
|
clock-names = "mac_core", "mac_ifc";
|
|
resets = <&crg 0xcc 8>,
|
|
<&crg 0xcc 10>,
|
|
<&gmacphyrst 0>;
|
|
reset-names = "mac_core", "mac_ifc", "phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac1: ethernet@9841000 {
|
|
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
|
|
reg = <0x9841000 0x1000>,
|
|
<0x9843010 0x4>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&crg HISTB_ETH1_MAC_CLK>,
|
|
<&crg HISTB_ETH1_MACIF_CLK>;
|
|
clock-names = "mac_core", "mac_ifc";
|
|
resets = <&crg 0xcc 9>,
|
|
<&crg 0xcc 11>,
|
|
<&gmacphyrst 1>;
|
|
reset-names = "mac_core", "mac_ifc", "phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
ir: ir@8001000 {
|
|
compatible = "hisilicon,hix5hd2-ir";
|
|
reg = <0x8001000 0x1000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&sysctrl HISTB_IR_CLK>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|