u-boot/board/freescale/common/qixis.h
Prabhakar Kushwaha 7d436078fe powerpc/t1040qds: Add T1040QDS board
T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
2013-10-16 16:15:16 -07:00

111 lines
2.9 KiB
C

/*
* Copyright 2011 Freescale Semiconductor
* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* This file provides support for the QIXIS of some Freescale reference boards.
*/
#ifndef __QIXIS_H_
#define __QIXIS_H_
struct qixis {
u8 id; /* ID value uniquely identifying each QDS board type */
u8 arch; /* Board version information */
u8 scver; /* QIXIS Version Register */
u8 model; /* Information of software programming model version */
u8 tagdata;
u8 ctl_sys;
u8 aux; /* Auxiliary Register,0x06 */
u8 clk_spd;
u8 stat_dut;
u8 stat_sys;
u8 stat_alrm;
u8 present;
u8 present2; /* Presence Status Register 2,0x0c */
u8 rcw_ctl;
u8 ctl_led;
u8 i2cblk;
u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
u8 rcfg_st;
u8 dcm_ad;
u8 dcm_da;
u8 dcmd;
u8 dmsg;
u8 gdc;
u8 gdd; /* DCM Debug Data Register,0x17 */
u8 dmack;
u8 res1[6];
u8 watch; /* Watchdog Register,0x1F */
u8 pwr_ctl[2]; /* Power Control Register,0x20 */
u8 res2[2];
u8 pwr_stat[4]; /* Power Status Register,0x24 */
u8 res3[8];
u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
u8 res4[2];
u8 sclk[3]; /* Clock Configuration Registers,0x34 */
u8 res5;
u8 dclk[3];
u8 res6;
u8 clk_dspd[3];
u8 res7;
u8 rst_ctl; /* Reset Control Register,0x40 */
u8 rst_stat; /* Reset Status Register */
u8 rst_rsn; /* Reset Reason Register */
u8 rst_frc[2]; /* Reset Force Registers,0x43 */
u8 res8[11];
u8 brdcfg[16]; /* Board Configuration Register,0x50 */
u8 dutcfg[16];
u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
u8 rcw_data;
u8 res9[5];
u8 post_ctl;
u8 post_stat;
u8 post_dat[2];
u8 pi_d[4];
u8 gpio_io[4];
u8 gpio_dir[4];
u8 res10[20];
u8 rjtag_ctl;
u8 rjtag_dat;
u8 res11[2];
u8 trig_src[4];
u8 trig_dst[4];
u8 trig_stat;
u8 res12[3];
u8 trig_ctr[4];
u8 res13[16];
u8 clk_freq[6]; /* Clock Measurement Registers */
u8 res_c6[8];
u8 clk_base[2]; /* Clock Frequency Base Reg */
u8 res_d0[8];
u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
u8 res_c0[6];
u8 aux2[4]; /* Auxiliary Registers,0xE0 */
u8 res14[10];
u8 aux_ad;
u8 aux_da;
u8 res15[16];
};
u8 qixis_read(unsigned int reg);
void qixis_write(unsigned int reg, u8 value);
u16 qixis_read_minor(void);
char *qixis_read_time(char *result);
char *qixis_read_tag(char *buf);
const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg);
void qixis_write_i2c(unsigned int reg, u8 value);
#endif
#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
#define QIXIS_WRITE_I2C(reg, value) \
qixis_write_i2c(offsetof(struct qixis, reg), value)
#endif
#endif