Poonam Aggrwal 82b7725b6d ppc/85xx: 32bit DDR changes for P1020/P1011 ... The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2009-09-24 12:04:59 -05:00
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config.mk	ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address	2009-09-09 21:04:47 -05:00
ddr.c	ppc/85xx: 32bit DDR changes for P1020/P1011	2009-09-24 12:04:59 -05:00
law.c	ppc/85xx: Clean up use of LAWAR defines	2009-09-24 12:04:58 -05:00
Makefile	85xx: Added PCIe support for P1 P2 RDB	2009-08-28 17:12:46 -05:00
p1_p2_rdb.c	85xx: Add support for P2020RDB board	2009-08-28 17:12:38 -05:00
pci.c	ppc/85xx: Clean up p1_p2_rdb PCI setup	2009-09-24 12:04:58 -05:00
tlb.c	85xx: Add support for P2020RDB board	2009-08-28 17:12:38 -05:00