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ARMADA 100 Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/applications/armada_100 SoC versions Supported: 1) ARMADA168/88AP168 (Aspen P) 2) ARMADA166/88AP166 (Aspen M) 3) ARMADA162/88AP162 (Aspen L) Contributors: Eric Miao <eric.y.miao@gmail.com> Lei Wen <leiwen@marvell.com> Mahavir Jain <mjain@marvell.com> Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _ARMADA100CPU_H
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#define _ARMADA100CPU_H
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#include <asm/io.h>
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#include <asm/system.h>
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/*
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* CPU Interface Registers
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* Refer Datasheet Appendix A.2
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*/
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struct armd1cpu_registers {
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u32 chip_id; /* Chip Id Reg */
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u32 pad;
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u32 cpu_conf; /* CPU Conf Reg */
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u32 pad1;
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u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
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u32 pad2;
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u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
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u32 mcb_conf; /* MCB Conf Reg */
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u32 sys_boot_ctl; /* Sytem Boot Control */
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};
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/*
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* Functions
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*/
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u32 armd1_sdram_base(int);
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u32 armd1_sdram_size(int);
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#endif /* _ARMADA100CPU_H */
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