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df8a24cdd3
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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extern void board_pll_init_f(void);
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/*
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* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
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*/
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void sdram_init(void)
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{
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return;
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}
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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static void cram_bcr_write(u32 wr_val)
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{
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wr_val <<= 2;
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/* set CRAM_CRE to 1 */
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gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
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/* Write BCR to CRAM on CS1 */
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out32(wr_val + 0x00200000, 0);
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debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
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/* Write BCR to CRAM on CS2 */
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out32(wr_val + 0x02200000, 0);
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debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
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sync();
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eieio();
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/* set CRAM_CRE back to 0 (normal operation) */
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gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
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return;
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}
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#endif
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long int initdram(int board_type)
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{
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#if defined(CONFIG_NAND_SPL)
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u32 reg;
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/* don't reinit PLL when booting via I2C bootstrap option */
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mfsdr(SDR_PINSTP, reg);
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if (reg != 0xf0000000)
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board_pll_init_f();
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#endif
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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int i;
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u32 val;
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/* 1. EBC need to program READY, CLK, ADV for ASync mode */
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gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
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gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
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gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
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gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
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/* 2. EBC in Async mode */
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mtebc(pb1ap, 0x078F1EC0);
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mtebc(pb2ap, 0x078F1EC0);
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mtebc(pb1cr, 0x000BC000);
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mtebc(pb2cr, 0x020BC000);
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/* 3. Set CRAM in Sync mode */
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cram_bcr_write(0x7012); /* CRAM burst setting */
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/* 4. EBC in Sync mode */
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mtebc(pb1ap, 0x9C0201C0);
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mtebc(pb2ap, 0x9C0201C0);
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/* Set GPIO pins back to alternate function */
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gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
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gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
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/* Config EBC to use RDY */
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mfsdr(sdrultra0, val);
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mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
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/* Wait a short while, since for NAND booting this is too fast */
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for (i=0; i<200000; i++)
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;
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#endif
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return (CFG_MBYTES_RAM << 20);
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}
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int testdram(void)
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{
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return (0);
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}
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